Renesas R5F5671CHDLK#20

Overview

R5F5671CHDLK#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI, smart metering, and secure IoT edge nodes.

For engineers reviewing the R5F5671CHDLK#20 datasheet, R5F5671CHDLK#20 pinout, R5F5671CHDLK#20 application, or R5F5671CHDLK#20 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-B (144-pin LQFP), functional pin roles, real-world use cases, and two validated alternative MCUs - all grounded in Renesas R01DS0373EJ0120 Rev.1.20.

Technical Context

The R5F5671CHDLK#20 implements the RXv3 CPU core with 113 instructions, 16 general-purpose 32-bit registers, and hardware-accelerated 32×32→64-bit multiply and 32/32→32-bit divide. Its double-precision FPU includes 16×64-bit data registers and 21 dedicated instructions, enabling deterministic floating-point computation for motor control and signal processing.

It integrates TSIP (Trusted Secure IP) with AES128/192/256, RSA, ECC, SHA256, TRNG, and key protection - certified for IEC60730 Class B compliance. Clock architecture supports independent domain scaling: ICLK up to 120 MHz, PCLKA up to 120 MHz (for MTU/RSPI/RIICHS), PCLKB up to 60 MHz (for most peripherals), and ADCLK up to 60 MHz per A/D unit.

Key Specifications

Pinout & Package

PLQP0144KA-B is a 144-pin LQFP package (20 × 20 mm, 0.50-mm pitch) with exposed thermal pad. Pin functions are defined per Renesas R01DS0373EJ0120 Table 1.2 and Figure 1.1 (Pin Assignment). All pins support 5-V tolerant inputs on 20 designated I/Os, open-drain outputs, and programmable pull-up resistors.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit industrial MCU applications.

Compared with R5F5671CHDLK#20, the R5F5670EHDLK#20 offers identical architecture and pin compatibility at reduced memory cost, while the R5F566TEHDFP#30 trades connectivity for enhanced motor control precision - making the R5F5671CHDLK#20 optimal for connected, secure, feature-rich industrial edge nodes.

Availability

R5F5671CHDLK#20 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, and secure IoT edge node designs requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for R5F5671CHDLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.

The RX671 Group targets secure, connected industrial devices - combining high-performance RXv3 execution, hardware cryptography (TSIP), and rich connectivity (CAN, USB, SDHI, QSPIX) for next-generation edge intelligence.

FAQ

What is the maximum operating frequency and CoreMark score of the R5F5671CHDLK#20?

The R5F5671CHDLK#20 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's single-cycle instruction execution, 16-register bank, and hardware multiplier/divider - enabling deterministic real-time response in industrial control loops. The R5F5671CHDLK#20 sustains this speed across its 384 KB SRAM and 2 MB flash with zero-wait access below 60 MHz and one-wait access up to 120 MHz.

Does the R5F5671CHDLK#20 support secure boot and cryptographic operations?

Yes, the R5F5671CHDLK#20 integrates Trusted Secure IP (TSIP) supporting AES-128/192/256, RSA, ECC, SHA256, MD5, GHASH, and a true-random number generator (TRNG). It provides hardware-enforced key protection and secure boot validation - meeting IEC60730 Class B requirements. These capabilities are accessible via Renesas' TSIP-Lite API and are used in the R5F5671CHDLK#20 for firmware signature verification, encrypted storage, and secure OTA updates without CPU overhead.

What package type and pin count does the R5F5671CHDLK#20 use?

The R5F5671CHDLK#20 uses the PLQP0144KA-B package: a 144-pin LQFP measuring 20 × 20 mm with 0.50-mm pitch and an exposed thermal pad. This package supports 113 general-purpose I/O pins (including 20 5-V tolerant inputs), full peripheral signal routing, and industrial-grade thermal dissipation. Pin assignments match Renesas' RX671 Group documentation (R01DS0373EJ0120), ensuring drop-in compatibility with existing RX671 reference designs.

Which communication interfaces are integrated into the R5F5671CHDLK#20?

The R5F5671CHDLK#20 integrates CAN (2 channels, 32 mailboxes each), USB 2.0 Full-Speed host/function/OTG, SD host interface (25 MB/s), Quad-SPI (QSPIX for serial flash fetch), three I²C channels (RIIC/RIICHS up to 3.4 Mbps), 13 SCI channels, 2 RSCI with Manchester encoding, and RSPI/RSPIA for SPI peripherals. These interfaces enable direct connectivity to industrial networks, memory cards, sensors, displays, and wireless modules - eliminating need for bridge ICs in the R5F5671CHDLK#20-based system.

How does the R5F5671CHDLK#20 support functional safety compliance?

The R5F5671CHDLK#20 includes multiple IEC60730 Class B-certifiable features: oscillation-stop detection, CRC-A accelerator, independent watchdog timer (IWDTa) with windowing, A/D converter self-diagnostic, memory protection unit (MPU), and register write protection. These are documented in Renesas' Functional Safety Manual (R01US0230EJ0200) and implemented in hardware - allowing developers to satisfy runtime diagnostics, fault detection, and recovery requirements without external components in the R5F5671CHDLK#20 design.