Renesas R5F5671CHDNE#30
- Part No.:
- R5F5671CHDNE#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
R5F5671CHDNE#30.pdf
- Description:
- IC MCU 32BIT 1.5MB FLASH 48WFQFN
- Quantity:
- Payment:

- Shipping:

Inventory:416
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5671CHDNE#30 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI, smart metering, and secure IoT edge nodes.
For engineers reviewing the R5F5671CHDNE#30 datasheet, R5F5671CHDNE#30 pinout, R5F5671CHDNE#30 application, or R5F5671CHDNE#30 equivalent, key selection criteria include its 120-MHz real-time performance (707 CoreMark), TSIP-based AES256/SHA256/RSA encryption, IEC60730-compliant safety features, and 114 GPIOs with 5-V tolerance - critical for functional safety and secure firmware updates.
Technical Context
The R5F5671CHDNE#30 implements the RXv3 CPU core with collective register bank save, memory protection unit (MPU), and JTAG/FINE debug interfaces. It integrates dual-clock domain operation: ICLK up to 120 MHz for CPU and QSPIX, and PCLKA/B/C/D up to 120/60/60/60 MHz respectively for peripherals including MTU3a timers, S12AD converters, and RIICHS.
Its peripheral architecture includes EXDMACa (2-channel extended DMA), DTCb (1-channel data transfer controller), and ELC (event link controller) enabling hardware-triggered, CPU-free sequencing between timers, ADCs, and communication modules - essential for deterministic real-time control and low-latency sensor-to-actuator response.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max - enables deterministic real-time execution with 707 CoreMark and single-cycle instruction throughput. |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k write cycles), 384 KB SRAM (no-wait @120 MHz). |
| FPU | Double-precision IEEE-754 coprocessor - supports high-accuracy motor control algorithms and floating-point math without software emulation. |
| Security | Trusted Secure IP (TSIP): AES128/192/256, RSA, ECC, SHA256, TRNG, and key protection - meets IEC60730 Class B and secure boot requirements. |
| Peripherals | 2× CAN FD-capable channels (32 mailboxes), 1× USB 2.0 FS host/function/OTG, 1× SDHI (25 MB/s), 1× QSPIX, 2× 12-bit S12AD (20 ch total), CTSU (64-key mutual cap). |
| Power & Temp | 2.7–3.6 V supply, –40°C to +85°C (D-version), four low-power modes including deep software standby with 4 KB backup RAM. |
| Package | PLQP0144KA-B: 144-pin LFQFP, 20 × 20 mm, 0.50-mm pitch - compatible with standard reflow and test fixtures for industrial PCB assembly. |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-Profile Quad Flat Package, 20 × 20 mm body, 0.50-mm lead pitch, RoHS-compliant, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains enable noise isolation for ADC and RTC; AVCC pins require dedicated filtering per datasheet layout guidelines. |
| VBATT | Backup power input | Supplies RTC, sub-clock oscillator, and backup registers during main power loss - enables tamper-resistant timekeeping and state retention. |
| RES# | Active-low reset input | Asynchronous hardware reset; internal POR/LVD ensures reliable initialization across voltage ramp-up and brownout conditions. |
| CLKIN / XTAL | Main clock input | Accepts 8–24 MHz crystal or external clock; PLL synthesizes 120 MHz ICLK - critical for timing-critical USB and SDHI synchronization. |
| USB_DP / USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates external PHY; supports host/function/OTG with 2 KB on-chip buffer - reduces BOM and board space. |
| SD0_CMD / SD0_CLK / SD0_DAT[0:3] | SD host interface signals | Direct 4-bit SD bus interface compliant with SD Physical Layer Spec v3.01 - enables local firmware updates via removable SD card. |
| CTSU_TX0–TX16 / CTSU_SOU0–SOU16 | Capacitive touch sensing electrodes | Supports 17 self-cap or 64 mutual-cap keys; hardware-accelerated CTSU engine offloads CPU and maintains low-power wake-on-touch. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with BGO | Enables seamless firmware updates: new image programmed in background while current code executes from active bank - zero-downtime field upgrades. |
| IEC60730-compliant safety suite | Includes oscillation-stop detection, CRC-A, IWDTa windowed watchdog, A/D self-diagnostic, and register write protection - certified for Class B functional safety. |
| Event Link Controller (ELC) | Hardware interconnects 99 internal events (e.g., timer overflow → ADC trigger → DMA transfer) - eliminates CPU polling and reduces interrupt latency to sub-microsecond. |
| TSIP cryptographic accelerator | Offloads AES256 encryption/decryption, SHA256 hashing, and RSA signing at hardware speed - secures OTA updates and device authentication without CPU overhead. |
| QSPIX serial flash fetch | Executes code directly from external quad-SPI flash (up to 32-bit addressing) - expands effective program memory beyond on-chip 2 MB while maintaining cache-like performance. |
Applications
| Industrial HMI Panel | Smart Electricity Meter |
|---|---|
|
Use Scenario: Touch-enabled front-panel display with real-time energy monitoring, tariff switching, and secure firmware updates. IC Role / Device Role / Timing Role: Main application MCU managing CTSU touch interface, SDHI for configuration logging, USB for field technician access, and TSIP for encrypted parameter storage. Use Value: Integrated 64-key mutual-cap CTSU eliminates external touch controller; dual-bank flash enables safe over-the-air updates without service interruption. |
Use Scenario: Revenue-grade meter with metrology processing, tamper detection, and DLMS/COSEM protocol stack execution. IC Role / Device Role / Timing Role: Real-time controller handling 12-bit dual S12AD sampling, RTC time-stamping, CAN communication with concentrator, and IEC60730 safety checks. Use Value: On-chip MPU and TSIP meet IEC62056-21 security requirements; VBATT-backed RTC ensures accurate billing timestamps during power outages. |
| Secure IoT Gateway | Motor Control Edge Node |
|
Use Scenario: Protocol-agnostic gateway aggregating Modbus, CAN, and BLE sensors, with TLS-secured cloud upload and local rule engine. IC Role / Device Role / Timing Role: Secure host processor running FreeRTOS, managing USB/SDHI for local diagnostics, CAN for fieldbus bridging, and TSIP for TLS handshake acceleration. Use Value: Hardware TRNG and AES256 reduce TLS handshake time by >80% vs. software-only; 114 GPIOs support flexible sensor expansion headers. |
Use Scenario: Compact BLDC drive with field-oriented control (FOC), real-time current sensing, and thermal protection. IC Role / Device Role / Timing Role: Real-time motion controller using MTU3a complementary PWM with dead-time insertion, S12AD for current feedback, and CMTW for precise timing loops. Use Value: 120 MHz RXv3 core delivers <1 µs loop jitter; integrated POE3a prevents shoot-through during fault conditions - no external gate driver logic required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EHDFP#30 | Same RX671 Group, 100-pin TFLGA, 1.5 MB flash, 256 KB SRAM, no SDHI or QSPIX - smaller footprint, lower peripheral count. | Suitable for cost-sensitive, space-constrained designs where SD card and external flash boot are not required. | Select when BOM cost and PCB area are prioritized over field-upgrade flexibility and large external code storage. |
| R5F572MDHDFB#30 | RX72M Group part: higher 240 MHz CPU, 4 MB flash, Ethernet MAC, but no CTSU or SDHI - targets networked PLCs, not touch HMI. | Used in industrial controllers requiring TCP/IP stack and deterministic EtherCAT, not capacitive touch or local media interfaces. | Choose only if Ethernet connectivity and higher compute throughput outweigh loss of touch sensing and SD/USB host capabilities. |
Compared with R5F5671CHDNE#30, the R5F5670EHDFP#30 sacrifices SDHI/QSPIX and memory capacity for compactness, while the R5F572MDHDFB#30 trades CTSU and media interfaces for Ethernet and higher clock speed - neither is pin-compatible, and both require PCB redesign and firmware adaptation.
Availability
R5F5671CHDNE#30 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, and secure IoT edge nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical deployments.
Supply support for R5F5671CHDNE#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets - with over 40 years of MCU innovation and ISO 26262/IEC 61508-certified development processes.
The RX671 Group is designed for high-integrity industrial applications demanding real-time performance, functional safety, and hardware security - targeting HMI, metering, and gateway systems where reliability, encryption, and mixed-signal integration are mandatory.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671CHDNE#30?
The R5F5671CHDNE#30 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark - measured under standard conditions with the RXv3 core executing the EEMBC benchmark. This performance level is sustained across its full temperature range (–40°C to +85°C) and supported by zero-wait-state access to 384 KB SRAM and optimized flash cache behavior.
Does the R5F5671CHDNE#30 support secure boot and cryptographic operations in hardware?
Yes, the R5F5671CHDNE#30 integrates Trusted Secure IP (TSIP) with hardware-accelerated AES128/192/256, SHA256, RSA, ECC, and a true random number generator (TRNG). It supports secure boot verification, encrypted firmware decryption, and TLS offload - all without CPU intervention, meeting IEC60730 Class B and Common Criteria EAL4+ requirements.
What package type and pin count does the R5F5671CHDNE#30 use?
The R5F5671CHDNE#30 uses the PLQP0144KA-B package: a 144-pin Low-Profile Quad Flat Package with 20 × 20 mm body size and 0.50-mm lead pitch. It provides 114 general-purpose I/O pins, including 20 with 5-V tolerance, and supports standard industrial reflow profiles and automated optical inspection (AOI).
Can the R5F5671CHDNE#30 execute code directly from external serial flash memory?
Yes, the R5F5671CHDNE#30 includes a QSPIX interface that supports direct execution (XIP) from external quad-SPI flash memory. It handles extended SPI, dual-SPI, and quad-SPI protocols with selectable address widths (8–32 bits), enabling scalable code storage beyond the on-chip 2 MB flash while maintaining deterministic timing via prefetch and cache mechanisms.
What safety certifications and diagnostic features does the R5F5671CHDNE#30 support?
The R5F5671CHDNE#30 includes IEC60730-compliant features such as oscillation-stop detection, CRC-A calculation unit, windowed independent watchdog timer (IWDTa), A/D converter self-diagnostic, and register write protection. These are implemented in hardware and documented in Renesas' Functional Safety Manual (R01US0174EJ0200), supporting Class B certification for industrial equipment.
R5F5671CHDNE#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-WFQFN Exposed Pad
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- I2C, LINbus, QSPI, SCI, SPI, UART/USART
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 33
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671CHDNE#30 FAQ
1.How can I place an order for R5F5671CHDNE#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671CHDNE#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671CHDNE#30 reliable?
The price and inventory of R5F5671CHDNE#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671CHDNE#30 is usually 5 days.
3.What payment methods are accepted for R5F5671CHDNE#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671CHDNE#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671CHDNE#30?
R5F5671CHDNE#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671CHDNE#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671CHDNE#30?
For technical support, including R5F5671CHDNE#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671CHDNE#30 requirements.
6.How does Aetrix verify that R5F5671CHDNE#30 is sourced from the original manufacturer or authorized distributors?
All R5F5671CHDNE#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671CHDNE#30 meets industry standards.
7.What is the process for return or replacement of R5F5671CHDNE#30?
All R5F5671CHDNE#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671CHDNE#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671CHDNE#30 part is unused and in its original packaging.
Return procedure for R5F5671CHDNE#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5671CHDNE#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

