Renesas R5F5671CHGFB#10

Overview

R5F5671CHGFB#10 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 2 Mbytes of dual-bank code flash, 384 Kbytes of zero-wait-state SRAM, and integrated capacitive touch sensing (CTSU) supporting up to 64 keys. It features USB 2.0 FS host/function/OTG, dual CAN 2.0B channels (32 mailboxes each), QSPIX for serial flash execution, SDHI (25 MB/s), and hardware encryption via TSIP (AES128/192/256, ECC, TRNG). Targeted for industrial HMI and secure connected edge devices requiring real-time control and tamper-resistant firmware.

For engineers reviewing the R5F5671CHGFB#10 datasheet, R5F5671CHGFB#10 pinout, R5F5671CHGFB#10 application, or R5F5671CHGFB#10 equivalent, key selection considerations include its 145-pin TFLGA (0.65-mm pitch) package, –40°C to +105°C operating range (G-version), IEC60730-compliant safety features (oscillation detection, CRC, self-diagnostic A/D), and dual-bank flash enabling safe firmware updates without halting operation.

Technical Context

The R5F5671CHGFB#10 implements the RXv3 CPU core with 113 instructions, including DSP and double-precision floating-point extensions, and supports little- or big-endian data arrangement. Its clock system integrates PLL, HOCO (16/18/20 MHz), LOCO (240 kHz), and sub-clock oscillator (32.768 kHz), with independent domain clocks (ICLK up to 120 MHz, PCLKA/B/C/D up to 120/60/60/60 MHz).

Peripheral subsystems include EXDMACa (2-channel extended DMA), DTCb (1-channel data transfer controller), and ELC (event link controller) enabling CPU-free inter-module triggering - e.g., MTU3a timer events directly initiating A/D conversions or CTSU scans. The TSIP security engine provides authenticated boot, key protection, and cryptographic acceleration compliant with FIPS 140-2 Level 1 requirements.

Key Specifications

Pinout & Package

Package: TFLGA-145 (PTLG0145JC-A), 9 × 9 mm body, 0.65-mm pitch, 145-terminal land grid array with exposed thermal pad. Pin count and I/O configuration match Table 1.2 in R01DS0373EJ0120: 111 general-purpose I/O pins, 20 with 5-V tolerance, all supporting pull-up, open-drain, and programmable drive strength.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit MCU applications.

Compared with R5F5671CHGFB#10, the R5F5670EHGFB#10 reduces memory and peripheral count for compact cost-sensitive nodes, while the R5F572MDHDFB#30 trades CTSU/TSIP for Ethernet and raw compute - making R5F5671CHGFB#10 optimal for touch-enabled, security-critical edge controllers where balanced performance, I/O, and trust are non-negotiable.

Availability

R5F5671CHGFB#10 is available at Aetrix Electronics and suitable for industrial HMI, secure gateways, smart energy meters, and medical diagnostic devices requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for R5F5671CHGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.

The RX671 Group is designed for high-integrity industrial edge devices demanding real-time responsiveness, functional safety (IEC60730), and hardware-rooted security - positioning R5F5671CHGFB#10 as a trusted platform for human-machine interfaces and connected infrastructure.

FAQ

What is the maximum operating frequency and CoreMark score of the R5F5671CHGFB#10?

The R5F5671CHGFB#10 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark points at that speed. This performance stems from the RXv3 CPU core's optimized pipeline, double-precision FPU, and zero-wait-state access to 384 Kbytes of SRAM - enabling deterministic real-time execution for industrial control loops and UI rendering.

Does the R5F5671CHGFB#10 support secure firmware updates, and how is it implemented?

Yes, the R5F5671CHGFB#10 supports secure firmware updates via its dual-bank flash architecture and Trusted Secure IP (TSIP). The dual-bank layout allows one bank to run active firmware while the other is reprogrammed; TSIP verifies digital signatures of new images using ECDSA before enabling bank swap - preventing unauthorized or corrupted code execution.

What package type and pin count does the R5F5671CHGFB#10 use, and what are its I/O capabilities?

The R5F5671CHGFB#10 uses a 145-pin TFLGA package (PTLG0145JC-A, 9 × 9 mm, 0.65-mm pitch) with 111 general-purpose I/O pins. Of these, 20 pins are 5-V tolerant, all support programmable pull-up resistors and open-drain outputs, and drive strength is configurable per port - simplifying interface to legacy 5-V logic and sensors.

How does the R5F5671CHGFB#10 meet IEC60730 Class B safety requirements?

The R5F5671CHGFB#10 meets IEC60730 Class B through integrated hardware safety mechanisms: oscillation-stop detection for clock failure, independent windowed watchdog timer (IWDTa), CRC calculation unit, self-diagnostic A/D converter, and register write protection. These features are documented in Renesas' IEC60730 compliance kit for the RX671 Group.

Can the R5F5671CHGFB#10 execute code directly from external serial flash memory?

Yes, the R5F5671CHGFB#10 supports execute-in-place (XIP) from external serial flash via its QSPIX interface. QSPIX handles extended SPI, dual-SPI, and quad-SPI protocols with 32-bit addressing, enabling fast, low-pin-count code storage - ideal for applications where on-chip flash capacity must be reserved for configuration or data logging.