Renesas R5F5671CHGFP#10
- Part No.:
- R5F5671CHGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F5671CHGFP#10.pdf
- Description:
- IC MCU 32BIT 1.5MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:3,603
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Product details
Overview
R5F5671CHGFP#10 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SDHI, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control and secure firmware updates.
For engineers reviewing the R5F5671CHGFP#10 datasheet, R5F5671CHGFP#10 pinout, R5F5671CHGFP#10 application, or R5F5671CHGFP#10 equivalent, key selection criteria include its 145-pin TFLGA (0.65-mm pitch) package, -40°C to +105°C G-grade temperature range, TSIP-based AES256/SHA256 encryption, and IEC60730-compliant self-diagnostic features for functional safety-critical firmware execution.
Technical Context
The R5F5671CHGFP#10 implements the RXv3 CPU core with 113 instructions, including DSP and floating-point extensions, and supports little-endian or big-endian data arrangement. Its clock system integrates PLL, sub-clock oscillator (32.768 kHz), and dedicated 120-kHz IWDT oscillator - enabling independent domain clocking: ICLK up to 120 MHz for CPU/QSPIX, PCLKA up to 120 MHz for MTU/RSPI, and PCLKB up to 60 MHz for most peripherals including S12AD units.
Memory architecture includes dual-bank 2 MB code flash (1-wait at 120 MHz), 8 KB data flash (100,000 write cycles), 384 KB zero-wait SRAM, and 4 KB standby RAM backed by VBATT. Peripheral interconnect uses Event Link Controller (ELC) to route 99 internal event signals - eliminating CPU intervention for timer-triggered ADC conversions, PWM dead-time compensation, or RTC time-capture on external events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark, double-precision FPU, MPU, 16 register banks |
| Memory | 2 MB code flash (dual-bank, BGO), 8 KB data flash (100K cycles), 384 KB SRAM (no wait), 4 KB standby RAM |
| Package & Temp | TFLGA-145 (9 × 9 mm, 0.65-mm pitch), G-grade: –40°C to +105°C |
| Peripherals | CAN ×2 (32 mailboxes/channel), USB 2.0 FS host/function/OTG, SDHI (25 MB/s), QSPIX (fetch from serial flash), RIICHS (3.4 Mbps) |
| Security & Safety | TSIP (AES128/192/256, RSA, ECC, TRNG, SHA256), IEC60730 self-test (CRC, IWDTa, A/D diag, OSC stop detection) |
| Analog & Timing | S12AD ×2 (8+12 ch, 0.48 µs/ch @12-bit), CTSU (17 self-cap or 64 mutual keys), RTC with battery backup, 25+ timers including MTU3a/TPUa |
Pinout & Package
Package: TFLGA-145 (PTLG0145JC-A), 9 × 9 mm, 0.65-mm pitch, 111 general-purpose I/O pins (20 with 5-V tolerance), 113 total I/O including dedicated power/ground and function-specific pins (USB D+/D−, CANH/CANL, SDIO lines, QSPIX signals).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog domains require 2.7–3.6 V; separate AVCC pins enable noise-isolated analog operation |
| VBATT | Backup power input | Supplies RTC, backup registers, and sub-clock oscillator during main power loss |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator for precise system clock generation |
| USB_DP/USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates external PHY; supports host/function/OTG without pull-up resistors |
| CANH/CANL | CAN bus differential outputs | ISO11898-1 compliant; each channel supports 32 mailboxes with hardware filtering |
| SD0_CMD/SD0_CLK/SD0_DAT[0:3] | SD host interface signals | 1- or 4-bit SD bus supporting SD memory/SDIO cards per Physical Layer Spec v3.01 |
| QSPIX_IO0–IO3 | Quad-SPI memory interface | Enables direct code/data fetch from external serial flash using quad-SPI protocol |
| CTSU_Sx (x=0–16) | Capacitive touch sensing inputs | Supports self-capacitance (17 keys) or mutual capacitance (64-key matrix) with built-in charge-transfer circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with BGO | Enables seamless firmware updates: execute from Bank A while programming Bank B, no runtime interruption |
| TSIP cryptographic engine | Hardware-accelerated AES256/SHA256/RSA/ECC prevents key extraction and ensures secure boot integrity |
| IEC60730 Class B compliance | Includes oscillator-stop detection, CRC-protected memory, IWDTa windowing, and A/D self-diagnostic for safety-certified designs |
| Event Link Controller (ELC) | Routes 99 internal events (e.g., TPU compare match → ADC start) without CPU overhead or interrupt latency |
| MTU3a complementary PWM | Generates non-overlapping 3-phase PWM with programmable dead time and automatic peak/trough suppression for motor control |
Applications
| Industrial HMI Panel | Smart Electricity Meter |
|---|---|
Use Scenario: Touch-enabled front-panel display with real-time energy monitoring, tariff switching, and tamper detection. IC Role / Device Role / Timing Role: Main application MCU handling capacitive touch (CTSU), LCD driving via GPIO/SPI, secure firmware updates (TSIP), and RTC-backed time-of-use billing. Use Value: Integrated CTSU eliminates external touch controller; dual-bank flash enables field-upgradable meter firmware without service interruption. | Use Scenario: Revenue-grade meter with isolation, PLC/RF communication, and anti-tampering logic. IC Role / Device Role / Timing Role: System controller managing isolated ADC sampling, CAN/RS485 comms, tamper-detection GPIOs, and secure key storage (TSIP). Use Value: IEC60730 self-tests ensure metrological integrity; 105°C rating supports operation inside sealed meter enclosures. |
| Home Energy Gateway | Factory Automation Node |
Use Scenario: Aggregating data from solar inverters, battery monitors, and smart appliances via CAN/USB/SDIO. IC Role / Device Role / Timing Role: Central hub MCU running Linux-compatible RTOS, interfacing with SD card (SDHI), USB peripherals, and CAN fieldbus. Use Value: QSPIX allows booting from external flash; SDHI supports local data logging; USB host enables plug-and-play dongle integration. | Use Scenario: Distributed I/O module with analog/digital sensor acquisition, PWM actuator control, and EtherCAT/PROFINET co-processor interface. IC Role / Device Role / Timing Role: Real-time motion controller executing PID loops via MTU3a PWM, sampling S12AD at 2 MSPS aggregate, and synchronizing via ELC-triggered ADC. Use Value: 120 MHz CPU + zero-wait SRAM delivers deterministic loop timing; 25+ timers support multi-axis coordination without software overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EHGFP#10 | Same RX671 Group, 145-pin TFLGA, but 1.5 MB flash, 256 KB SRAM, no SDHI or QSPIX | Lacks SD host and quad-SPI interfaces; suitable for CAN/USB-only edge nodes without local storage | Select when SDHI/QSPIX are unnecessary and cost reduction is prioritized over memory headroom |
| R5F566TEHGFP#10 | RX66T Group, same package, 160 MHz CPU, 1 MB flash, 192 KB SRAM, no TSIP or CTSU | Optimized for motor control (3 MTU units, 3-phase PWM), lacks crypto/touch but adds higher PWM resolution | Prefer for servo drives or inverters where real-time PWM precision outweighs security/touch needs |
Compared with R5F5670EHGFP#10, the R5F5671CHGFP#10 adds SDHI and QSPIX for local data logging and external code execution, while versus R5F566TEHGFP#10 it trades motor-control specialization for broader connectivity and embedded security - making it optimal for connected, safety-aware HMI and metering endpoints.
Availability
R5F5671CHGFP#10 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, home energy gateways, and factory automation nodes requiring stable component supply across extended temperature and long product lifecycles.
Supply support for R5F5671CHGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX671 Group targets high-integrity industrial applications demanding real-time performance, functional safety certification (IEC60730), and secure connectivity - with R5F5671CHGFP#10 optimized for G-grade environments requiring extended temperature operation and cryptographic firmware protection.
FAQ
What is the maximum operating frequency and CPU architecture of the R5F5671CHGFP#10?
The R5F5671CHGFP#10 features a 32-bit RXv3 CPU core with a maximum operating frequency of 120 MHz, achieving 707 CoreMark. It supports double-precision IEEE-754 floating-point operations, 113 instructions (including DSP and floating-point extensions), and selectable little-endian or big-endian data arrangement - all implemented in the R5F5671CHGFP#10's silicon die.
Does the R5F5671CHGFP#10 support secure firmware updates and cryptographic functions?
Yes, the R5F5671CHGFP#10 integrates Trusted Secure IP (TSIP) providing hardware-accelerated AES128/192/256, RSA, ECC, SHA256, and a true-random number generator. Its dual-bank flash supports background programming (BGO), enabling secure over-the-air updates where R5F5671CHGFP#10 executes from one bank while writing to the other - ensuring zero downtime and tamper-resistant key storage.
What peripheral interfaces does the R5F5671CHGFP#10 include for industrial connectivity?
The R5F5671CHGFP#10 includes CAN ×2 (ISO11898-1, 32 mailboxes/channel), USB 2.0 FS host/function/OTG, SD host interface (SDHI) supporting 25 MB/s, Quad-SPI (QSPIX) for serial flash fetch, and high-speed I²C (RIICHS, 3.4 Mbps). These interfaces are fully integrated into the R5F5671CHGFP#10's pinout and clock domains without requiring external transceivers or level shifters.
How does the R5F5671CHGFP#10 meet IEC60730 Class B requirements for functional safety?
The R5F5671CHGFP#10 meets IEC60730 Class B through on-chip features including oscillation-stoppage detection, CRC-protected memory, windowed independent watchdog timer (IWDTa), self-diagnostic A/D converter test, and register write protection. These capabilities are documented in the R5F5671CHGFP#10 datasheet (R01DS0373EJ0120) and validated for use in safety-critical firmware execution.
What is the package type, pin count, and temperature grade of the R5F5671CHGFP#10?
The R5F5671CHGFP#10 uses a 145-pin TFLGA package (PTLG0145JC-A, 9 × 9 mm, 0.65-mm pitch) rated for the G-grade industrial temperature range of –40°C to +105°C. It provides 111 general-purpose I/O pins (20 with 5-V tolerance), matching the mechanical and thermal specifications defined for the R5F5671CHGFP#10 in Renesas' official documentation.
R5F5671CHGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 80
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671CHGFP#10 FAQ
1.How can I place an order for R5F5671CHGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671CHGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671CHGFP#10 reliable?
The price and inventory of R5F5671CHGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671CHGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F5671CHGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671CHGFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671CHGFP#10?
R5F5671CHGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671CHGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671CHGFP#10?
For technical support, including R5F5671CHGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671CHGFP#10 requirements.
6.How does Aetrix verify that R5F5671CHGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F5671CHGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671CHGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F5671CHGFP#10?
All R5F5671CHGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671CHGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671CHGFP#10 part is unused and in its original packaging.
Return procedure for R5F5671CHGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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