Renesas R5F5671CHGLJ#20

Overview

R5F5671CHGLJ#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart sensor edge nodes requiring deterministic real-time control and secure firmware updates.

For engineers reviewing the R5F5671CHGLJ#20 datasheet, R5F5671CHGLJ#20 pinout, R5F5671CHGLJ#20 application, or R5F5671CHGLJ#20 equivalent, this page delivers verified package mapping (PLQP0144KA-B, 144-pin LQFP), confirmed peripheral channel counts (2× CAN, 13× SCI, 2× RIIC/RIICHS), exact clock domain assignments (ICLK ≤ 120 MHz, PCLKA ≤ 120 MHz, PCLKB ≤ 60 MHz), and validated security features including TSIP with AES256, TRNG, and IEC60730-compliant self-diagnostic functions.

Technical Context

The R5F5671CHGLJ#20 implements the RXv3 CPU core with collective register bank save, memory protection unit (MPU), and JTAG/FINE debug interfaces. Its clock system supports external crystal (8–24 MHz), sub-clock (32.768 kHz), and internal oscillators (LOCO/HOCO/IWDT-dedicated), with independent frequency division for ICLK, PCLKA–PCLKD, FCLK, and BCLK domains.

Peripheral integration includes DMACAb (8-channel), EXDMACa (2-channel), DTCb (1-channel), MTU3a (9-channel timer with complementary PWM), TPUa (6-channel), CMT/CMTW timers, S12ADFa dual 12-bit ADCs (8+12 channels), and CTSUa capacitive touch unit supporting 17 self-capacitance keys or 64 mutual-capacitance keys - all coordinated via the Event Link Controller (ELC) for hardware-triggered, CPU-free operation.

Key Specifications

Pinout & Package

Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package (20 × 20 mm, 0.50-mm pitch), RoHS-compliant, lead-free, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit industrial MCU applications.

Compared with R5F5671CHGLJ#20, the R5F5670EHGLJ#20 reduces I/O count and removes SDHI/QSPIX to lower cost and size, while the R5F566T7HDFP#30 trades TSIP and capacitive touch for enhanced motor control peripherals and higher clock speed - making each alternative optimal only within its specific subsystem context.

Availability

R5F5671CHGLJ#20 is available at Aetrix Electronics and suitable for industrial HMI, smart sensor nodes, secure gateways, and motor control interfaces requiring stable component supply, long-term lifecycle assurance, and full technical documentation support.

Supply support for R5F5671CHGLJ#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader delivering trusted microcontrollers, analog, power, and SoC solutions for automotive, industrial, infrastructure, and IoT markets.

The RX671 Group, including R5F5671CHGLJ#20, is engineered for industrial edge devices requiring real-time determinism, functional safety support (IEC60730), and hardware security - balancing performance, peripheral richness, and robustness in harsh environments.

FAQ

What is the maximum operating frequency and core architecture of the R5F5671CHGLJ#20?

The R5F5671CHGLJ#20 operates at a maximum frequency of 120 MHz using the 32-bit RXv3 CPU core. It delivers 707 CoreMark performance and includes double-precision IEEE-754 floating-point support, collective register bank save, and a memory protection unit (MPU). The core supports little-endian instruction/data layout and offers 113 instructions including DSP and floating-point operations - all confirmed in the official R01DS0373EJ0120 datasheet Rev.1.20.

Does the R5F5671CHGLJ#20 support secure firmware updates and cryptographic acceleration?

Yes, the R5F5671CHGLJ#20 integrates Trusted Secure IP (TSIP) providing hardware-accelerated AES128/192/256, SHA256, RSA, ECC, and a true random number generator (TRNG). It supports secure boot, encrypted firmware updates, and key protection - validated by Renesas' IEC60730 Class B self-test suite and documented in the R5F5671CHGLJ#20 datasheet Section 1.1 and Security chapter.

What package type and pin count does the R5F5671CHGLJ#20 use?

The R5F5671CHGLJ#20 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package measuring 20 × 20 mm with 0.50-mm pitch. It provides 114 general-purpose I/O pins, of which 20 are 5-V tolerant - matching the pinout definition in Table 1.2 of the R01DS0373EJ0120 datasheet and confirmed on Renesas' official product page for RX671 Group devices.

Which communication interfaces are integrated into the R5F5671CHGLJ#20?

The R5F5671CHGLJ#20 integrates dual CAN 2.0B (ISO11898-1), USB 2.0 Full-Speed host/function/OTG, SD host interface (25 MB/s), Quad-SPI (QSPIX) for serial flash boot, 13-channel SCI (asynchronous/clock-synchronous/LIN), 3-channel RIIC/RIICHS (up to 3.4 Mbps), and 4-channel SPI (RSPId/RSPIA). All interfaces are electrically and functionally verified per R01DS0373EJ0120 Rev.1.20 Sections 1.1 and 7–9.

How does the R5F5671CHGLJ#20 support low-power operation in battery-backed applications?

The R5F5671CHGLJ#20 supports four low-power modes - Sleep, All-module Clock Stop, Software Standby, and Deep Software Standby - with VBATT pin enabling backup power for RTC, sub-clock oscillator, and 4 KB standby RAM. This allows continuous timekeeping and context retention during main power loss, as specified in Section 1.1 "Low power consumption function" and Section 5.3 "Battery backup function" of the R01DS0373EJ0120 datasheet.