Renesas R5F5671EDDBP#20
- Part No.:
- R5F5671EDDBP#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-TFBGA
- Datasheet:
-
R5F5671EDDBP#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 64TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:490
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Product details
Overview
R5F5671EDDBP#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI, smart metering, and connected appliance control systems.
For engineers reviewing the R5F5671EDDBP#20 datasheet, R5F5671EDDBP#20 pinout, R5F5671EDDBP#20 application, or R5F5671EDDBP#20 equivalent, key selection considerations include its 145-pin TFLGA (0.65-mm pitch) package, IEC60730-compliant safety features including TSIP encryption and self-diagnostic A/D, RTC with battery backup, and low-power deep software standby mode supporting 4 KB standby RAM.
Technical Context
The R5F5671EDDBP#20 implements the RXv3 CPU core with 113 instructions, 16 general-purpose 32-bit registers, and dual-precision FPU supporting 21 double-precision floating-point instructions. It integrates an event link controller (ELC) enabling hardware-triggered peripheral coordination without CPU intervention.
Its clock system combines external crystal (8–24 MHz), sub-clock (32.768 kHz), and internal oscillators (LOCO at 240 kHz, HOCO at 16/18/20 MHz), with independent frequency domains: ICLK up to 120 MHz for CPU/QSPIX, PCLKA up to 120 MHz for MTU/RSPI/RIICHS, and PCLKB up to 60 MHz for most peripherals and ADCLK.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark score - enables real-time deterministic control with high computational throughput. |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k write cycles), 384 KB SRAM (no-wait at 120 MHz) - supports robust firmware updates and large buffer handling. |
| Analog Peripherals | Two 12-bit A/D units (8+12 channels), on-die temperature sensor (±1°C), CTSU with 17 self-capacitance keys - enables precision sensing and touch HMI without external components. |
| Connectivity | CAN v2.0B (2 channels, 32 mailboxes), USB 2.0 FS host/function/OTG, SDHI (25 MB/s), QSPIX (fetch from serial flash), RIICHS (3.4 Mbps) - delivers full-stack embedded connectivity for industrial edge nodes. |
| Security & Safety | Trusted Secure IP (TSIP) with AES128/192/256, RSA, ECC, TRNG, SHA256, and IEC60730 compliance features (oscillation detection, CRC, IWDT, A/D self-test) - meets functional safety and secure boot requirements. |
| Package & Environment | TFLGA-145 (9 × 9 mm, 0.65-mm pitch), –40°C to +85°C (D-version), 111 GPIOs with 5-V tolerance and configurable drive strength - suited for compact, rugged industrial PCB layouts. |
Pinout & Package
Package: TFLGA-145 (9 × 9 mm, 0.65-mm pitch), 111 general-purpose I/O pins, 1 dedicated input pin, 111 pull-up resistors, 111 open-drain outputs, 20 5-V tolerant pins, VBATT and VCC pins for battery-backed RTC operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | 2.7–3.6 V single-supply operation; AVCC0/AVCC1 power ADC and analog circuits with independent filtering. |
| VBATT | Backup power input | Enables RTC, backup registers, and sub-clock oscillator during main power loss - critical for timekeeping in energy meters. |
| RES# | Active-low reset input | Hardware reset assertion; combined with internal POR and LVD for robust power-on and brownout recovery. |
| EXTAL / XTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system timing and USB clock derivation via PLL. |
| EXCLK | External clock input | Accepts up to 30 MHz external clock source as alternative to crystal - simplifies timing design in noise-sensitive environments. |
| MD0 / MD1 | Mode setting pins | Determine boot mode (SCI/USB/FINE) and operating mode (single-chip/extended) at reset release - configure initial firmware load path. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating downtime during field upgrades. |
| Event Link Controller (ELC) | Hardware interconnect between 99 internal events (e.g., timer overflow → A/D trigger → DMA transfer) - reduces CPU overhead and interrupt latency. |
| Capacitive Touch Sensing Unit (CTSU) | Supports 17-key self-capacitance or 64-key mutual-capacitance matrix - enables robust, low-EMI touch interfaces without external ICs. |
| IEC60730-compliant safety suite | Includes oscillation-stop detection, CRC calculation unit, IWDT windowing, A/D self-diagnostic, and register write protection - accelerates Class B certification. |
| SD host interface (SDHI) | Full-speed SD/SDIO support (25 MB/s, 1-/4-bit bus, CRC7/CRC16) - enables local data logging, firmware storage, and peripheral expansion (Wi-Fi/BT modules). |
Applications
| Industrial HMI Panel | Smart Energy Meter |
|---|---|
Use Scenario: Touch-enabled display panel with real-time data visualization, local configuration, and CAN/USB diagnostics in factory automation. IC Role / Device Role / Timing Role: Main application MCU managing GUI rendering, capacitive touch decoding, CAN bus communication, and USB device enumeration. Use Value: Integrated CTSU eliminates external touch controller; dual-bank flash enables safe over-the-air updates; TSIP secures firmware integrity. |
Use Scenario: Revenue-grade electricity meter requiring tamper detection, RTC-based billing, and secure firmware updates over PLC or RF links. IC Role / Device Role / Timing Role: System controller handling metrology interface, RTC with battery backup, secure boot, and encrypted communication stack. Use Value: VBATT-powered RTC maintains time across outages; TSIP AES/RSA protects firmware; IEC60730 features satisfy utility certification requirements. |
| Connected Home Appliance | Building Automation Node |
Use Scenario: Wi-Fi/BLE gateway appliance (e.g., HVAC controller) with local UI, sensor aggregation, and cloud sync via USB/SD card. IC Role / Device Role / Timing Role: Central MCU coordinating touch UI, SDHI-based log storage, USB host for dongle-based connectivity, and QSPIX for fast boot from serial flash. Use Value: QSPIX enables instant boot and XIP execution; SDHI supports field-serviceable firmware backups; USB host powers and manages wireless modules. |
Use Scenario: DIN-rail mounted controller interfacing with BACnet MS/TP, Modbus RTU, and KNX via isolated RS-485 transceivers and CAN. IC Role / Device Role / Timing Role: Protocol bridge MCU running multiple serial stacks (SCIh/SCIk/RSCI), CAN gateway logic, and real-time scheduling via MTU3a timers. Use Value: 13 SCI channels and 2 CAN controllers enable concurrent multi-protocol support; ELC synchronizes serial framing with timer-triggered sampling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EDDBP#20 | Same RX671 Group, identical 145-pin TFLGA package, but with 1 MB code flash and 256 KB SRAM - no dual-bank flash or TSIP. | Lacks TSIP encryption and dual-bank update capability; suitable only where security and zero-downtime updates are not required. | Select when cost sensitivity outweighs firmware security and field upgrade flexibility. |
| R5F566TEADFP#30 | RX66T Group part in 144-pin LFQFP; 160 MHz CPU, 1 MB flash, no TSIP, no SDHI, no QSPIX, but enhanced PWM (3-phase inverter control focus). | Optimized for motor control with MTU3b and POE3b; lacks SD/USB/QSPIX - unsuitable for data logging or host connectivity. | Choose only for inverter-driven applications needing higher PWM resolution and phase control, not for HMI or secure connectivity. |
Compared with R5F5671EDDBP#20, the R5F5670EDDBP#20 offers lower memory and no security features, while the R5F566TEADFP#30 trades connectivity and security for motor-control peripherals - making R5F5671EDDBP#20 uniquely balanced for secure, connected industrial edge devices.
Availability
R5F5671EDDBP#20 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, and building automation applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F5671EDDBP#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX671 Group, including R5F5671EDDBP#20, is designed for secure, connected industrial edge applications demanding real-time performance, functional safety, and rich peripheral integration - especially where HMI, data logging, and field-upgradable firmware are essential.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671EDDBP#20?
The R5F5671EDDBP#20 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark in benchmark testing. This performance stems from its RXv3 CPU core with optimized instruction pipeline and dual-precision FPU - enabling deterministic real-time execution for industrial control loops and signal processing tasks within the R5F5671EDDBP#20.
Does the R5F5671EDDBP#20 support secure firmware updates and cryptographic operations?
Yes, the R5F5671EDDBP#20 integrates Trusted Secure IP (TSIP) supporting AES128/192/256, RSA, ECC, SHA256, and a true random number generator. Its dual-bank flash architecture allows background programming of one bank while executing from the other - enabling authenticated, encrypted, and zero-downtime firmware updates in the R5F5671EDDBP#20.
What package type and pin count does the R5F5671EDDBP#20 use?
The R5F5671EDDBP#20 uses a 145-pin TFLGA package measuring 9 × 9 mm with 0.65-mm pitch. It provides 111 general-purpose I/O pins, 20 of which are 5-V tolerant, along with dedicated VBATT, RES#, and crystal terminals - matching the mechanical and thermal requirements of space-constrained industrial PCBs using the R5F5671EDDBP#20.
Can the R5F5671EDDBP#20 operate with battery backup for RTC functionality?
Yes, the R5F5671EDDBP#20 supports battery backup via the VBATT pin to maintain RTC operation, backup registers, and sub-clock oscillator during main power loss. This ensures continuous timekeeping and state retention in energy meters and alarm systems - a confirmed capability of the R5F5671EDDBP#20 per its datasheet Section 1.1 and electrical characteristics table.
Which communication interfaces are integrated into the R5F5671EDDBP#20?
The R5F5671EDDBP#20 integrates CAN (2 channels, 32 mailboxes), USB 2.0 FS host/function/OTG, SD host interface (25 MB/s), QSPIX (serial flash fetch), RIICHS (3.4 Mbps), and 13 serial channels (SCI/SCIm/RSCI). These interfaces collectively enable the R5F5671EDDBP#20 to serve as a central connectivity hub in industrial edge devices without external protocol translators.
R5F5671EDDBP#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-TFBGA
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 43
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 10x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EDDBP#20 FAQ
1.How can I place an order for R5F5671EDDBP#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EDDBP#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EDDBP#20 reliable?
The price and inventory of R5F5671EDDBP#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EDDBP#20 is usually 5 days.
3.What payment methods are accepted for R5F5671EDDBP#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671EDDBP#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671EDDBP#20?
R5F5671EDDBP#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671EDDBP#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EDDBP#20?
For technical support, including R5F5671EDDBP#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EDDBP#20 requirements.
6.How does Aetrix verify that R5F5671EDDBP#20 is sourced from the original manufacturer or authorized distributors?
All R5F5671EDDBP#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EDDBP#20 meets industry standards.
7.What is the process for return or replacement of R5F5671EDDBP#20?
All R5F5671EDDBP#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EDDBP#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EDDBP#20 part is unused and in its original packaging.
Return procedure for R5F5671EDDBP#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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