Renesas R5F5671EDDLE#20
- Part No.:
- R5F5671EDDLE#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F5671EDDLE#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5671EDDLE#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SDHI, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control and secure firmware updates.
For engineers reviewing the R5F5671EDDLE#20 datasheet, R5F5671EDDLE#20 pinout, R5F5671EDDLE#20 application, or R5F5671EDDLE#20 equivalent, key selection criteria include its 145-pin TFLGA (0.65-mm pitch) package, IEC60730-compliant safety features (TSIP, CRC, IWDTa, self-diagnostic A/D), and hardware-accelerated crypto (AES128/192/256, ECC, TRNG).
Technical Context
The R5F5671EDDLE#20 implements the RXv3 CPU core with collective register bank save, memory protection unit (MPU), and JTAG/FINE debug interfaces. Its clock system integrates PLL, sub-clock oscillator (32.768 kHz), and dedicated 120-kHz IWDTa oscillator - enabling deterministic timing for safety-critical tasks.
Peripheral subsystems include dual 12-bit A/D converters (8+12 channels), MTU3a (9-channel timer with complementary PWM), CTSUa (17-key self-capacitance or 64-key mutual-capacitance touch), and TSIP-based encryption supporting AES, ECC, SHA256, and true random number generation - all synchronized to independent clock domains (ICLK up to 120 MHz, PCLKA/B up to 120/60 MHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max - enables 707 CoreMark performance and deterministic real-time execution. |
| Memory | 2 MB code flash (dual-bank), 384 KB SRAM, 8 KB data flash - supports background programming and firmware swapping without reset. |
| FPU | Double-precision IEEE-754 coprocessor - accelerates floating-point math for motor control and sensor fusion algorithms. |
| Security | Trusted Secure IP (TSIP) with AES128/192/256, ECC, TRNG, and register write protection - meets IEC60730 Class B requirements. |
| Interfaces | CAN (2 ch, 32 mailboxes), USB 2.0 FS host/function, SDHI (25 MB/s), QSPIX (quad-SPI fetch), RIICHS (3.4 Mbps) - enables connectivity in embedded gateways. |
| Package | PTLG0145JC-A: 145-pin TFLGA, 9 × 9 mm, 0.65-mm pitch - provides 111 GPIOs with 5-V tolerance and configurable drive strength. |
| Temp Range | –40°C to +85°C (D-version) - qualified for industrial ambient operation without derating. |
Pinout & Package
PTLG0145JC-A is a 145-pin Thin Fine-Pitch Land Grid Array (TFLGA) package measuring 9 × 9 mm with 0.65-mm pitch, optimized for high-density PCB layouts and thermal dissipation in sealed industrial enclosures.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Single 2.7–3.6 V rail powers CPU, peripherals, and ADCs; AVCC pins isolate analog noise for 12-bit conversion accuracy. |
| VBATT | Backup power input | Enables RTC and backup registers to retain state during main power loss - critical for energy meter time-stamping. |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external resonator for precise system clock generation and USB timing compliance. |
| USB_DP / USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates external PHY; supports host, device, and OTG modes with 2 KB on-chip buffer. |
| SD_CLK / SD_CMD / SD_DAT[0:3] | SD host interface signals | Direct connection to SD/SDIO cards at 25 MB/s (high-speed mode); includes CRC7/CRC16 error checking and DMA support. |
| CTSU_Sx / CTSU_SO | Capacitive touch sensing inputs | 17 dedicated pins for self-capacitance keys or matrix scan - enables robust touch HMI without external controllers. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed - zero downtime in field-deployed devices. |
| IEC60730 safety suite | Includes oscillation-stop detection, CRC accelerator, IWDTa with window function, and A/D self-diagnostic - reduces certification effort for household appliances. |
| Event Link Controller (ELC) | Hardware interconnects 99 internal events (e.g., timer overflow → ADC trigger → DMA transfer) - eliminates CPU polling and reduces latency by >90%. |
| MTU3a complementary PWM | Generates non-overlapping 3-phase gate drive waveforms with programmable dead time - directly controls inverters in HVAC and motor drives. |
| TSIP cryptographic engine | Offloads AES/ECC/SHA operations from CPU; prevents key extraction via side-channel attacks - secures OTA firmware delivery. |
Applications
| Industrial HMI Panels | Smart Energy Meters |
|---|---|
Use Scenario: Touch-enabled operator interface with real-time data visualization and local configuration. IC Role / Device Role / Timing Role: Main application processor executing GUI stack, managing CTSU touch inputs, and driving SPI/QSPIX-connected display memory. Use Value: Integrated 17-key CTSU eliminates external touch controller; dual-bank flash enables silent firmware upgrades during idle periods. | Use Scenario: Revenue-grade electricity meter with time-of-use billing, tamper detection, and remote firmware update capability. IC Role / Device Role / Timing Role: System-on-chip handling metrology (via S12AD), RTC timestamping, secure communication (CAN/USB), and encrypted firmware validation. Use Value: TSIP-based AES256 and TRNG ensure firmware authenticity; VBATT-backed RTC maintains accurate billing timestamps during power outages. |
| Home Automation Gateways | Motor Control Drives |
Use Scenario: Protocol-bridging hub connecting Zigbee/Z-Wave sensors to cloud via Ethernet/Wi-Fi (external PHY). IC Role / Device Role / Timing Role: Central protocol translator with USB host (for dongles), CAN (for legacy HVAC), SDHI (for logging), and QSPIX (for boot firmware). Use Value: Dual CAN channels and USB 2.0 FS support simultaneous legacy and modern peripheral integration without external bridges. | Use Scenario: Variable-frequency drive for HVAC compressors requiring precise PWM timing and fault protection. IC Role / Device Role / Timing Role: Real-time motion controller generating complementary PWM (MTU3a), sampling current/voltage (S12AD), and executing field-oriented control (RXv3 FPU). Use Value: Hardware-accelerated 3-phase PWM with auto-dead-time insertion prevents shoot-through; 120 MHz CPU sustains 20 kHz control loop rates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EDDLE#20 | Same RX671 family, 1 MB flash, 256 KB SRAM, identical pinout and peripheral set - lower memory density. | Suitable for cost-sensitive designs where 2 MB flash and 384 KB SRAM are not required. | Select when firmware size remains under 1 MB and RAM usage stays below 256 KB to reduce BOM cost. |
| R5F566TEADD#20 | RX66T group; 160 MHz CPU, 1 MB flash, 192 KB SRAM, no TSIP or CTSU; adds encoder interface and higher PWM resolution. | Optimized for servo/motor control with position feedback - lacks security and touch features of R5F5671EDDLE#20. | Choose for high-performance motor drives needing encoder input and faster PWM, but omit if IEC60730 or HMI touch are mandatory. |
Compared with R5F5671EDDLE#20, R5F5670EDDLE#20 offers identical safety and interface capabilities at reduced memory cost, while R5F566TEADD#20 trades security and touch for enhanced motor-control peripherals - making R5F5671EDDLE#20 the optimal choice for secure, touch-enabled industrial edge nodes.
Availability
R5F5671EDDLE#20 is available at Aetrix Electronics and suitable for industrial HMI panels, smart energy meters, home automation gateways, and motor control drives requiring stable component supply across multi-year production cycles.
Supply support for R5F5671EDDLE#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RX671 Group targets high-integrity industrial applications demanding functional safety (IEC60730), secure firmware execution (TSIP), and rich human-machine interaction (CTSU, USB, SDHI) - all within a single-chip solution.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671EDDLE#20?
The R5F5671EDDLE#20 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark performance. This benchmark reflects its RXv3 CPU core efficiency, double-precision FPU, and optimized memory subsystem - enabling real-time processing in demanding industrial applications. The R5F5671EDDLE#20 sustains this performance across its full temperature range without throttling.
Does the R5F5671EDDLE#20 support secure boot and firmware encryption?
Yes, the R5F5671EDDLE#20 integrates Trusted Secure IP (TSIP) supporting AES128/192/256, ECC, SHA256, and a true random number generator (TRNG). It enables secure boot verification, encrypted firmware storage, and runtime key protection - meeting IEC60730 Class B requirements. These features are implemented in hardware and accessible via Renesas' Secure Boot Manager, ensuring the R5F5671EDDLE#20 resists cloning and unauthorized firmware modification.
What package type and pin count does the R5F5671EDDLE#20 use?
The R5F5671EDDLE#20 uses the PTLG0145JC-A package: a 145-pin Thin Fine-Pitch Land Grid Array measuring 9 × 9 mm with 0.65-mm pitch. It provides 111 general-purpose I/O pins, including 20 with 5-V tolerance, and supports high-density PCB routing. This package is confirmed in the official Renesas datasheet R01DS0373EJ0120 and matches the "DDLE" suffix designation.
Can the R5F5671EDDLE#20 interface directly with SD cards and serial flash memory?
Yes, the R5F5671EDDLE#20 includes a dedicated SD host interface (SDHI) supporting 1- and 4-bit SD/SDIO buses at up to 25 MB/s, and a Quad-SPI memory interface (QSPIX) that supports extended SPI, dual-SPI, and quad-SPI protocols for direct code fetching from serial flash. Both interfaces feature hardware CRC, DMA support, and error recovery - eliminating external glue logic when using R5F5671EDDLE#20 in data-logging or boot-from-flash designs.
What safety certifications and diagnostic features does the R5F5671EDDLE#20 support?
The R5F5671EDDLE#20 includes built-in features for IEC60730 Class B compliance: oscillation-stop detection, CRC accelerator, independent watchdog timer (IWDTa) with window function, self-diagnostic A/D converter, and register write protection. These are hardware-implemented and documented in the R01DS0373EJ0120 datasheet. The R5F5671EDDLE#20 also supports MPU-based memory protection and TSIP-based secure key management - collectively reducing software certification burden for household and industrial appliances.
R5F5671EDDLE#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EDDLE#20 FAQ
1.How can I place an order for R5F5671EDDLE#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EDDLE#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EDDLE#20 reliable?
The price and inventory of R5F5671EDDLE#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EDDLE#20 is usually 5 days.
3.What payment methods are accepted for R5F5671EDDLE#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671EDDLE#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671EDDLE#20?
R5F5671EDDLE#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671EDDLE#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EDDLE#20?
For technical support, including R5F5671EDDLE#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EDDLE#20 requirements.
6.How does Aetrix verify that R5F5671EDDLE#20 is sourced from the original manufacturer or authorized distributors?
All R5F5671EDDLE#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EDDLE#20 meets industry standards.
7.What is the process for return or replacement of R5F5671EDDLE#20?
All R5F5671EDDLE#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EDDLE#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EDDLE#20 part is unused and in its original packaging.
Return procedure for R5F5671EDDLE#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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