My Inquiry
My Account
Renesas R5F5671EDGFB#10
- Part No.:
- R5F5671EDGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5671EDGFB#10.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,949
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5671EDGFB#10 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 2-MB on-chip code flash (dual-bank), 384-KB SRAM, and integrated capacitive touch sensing unit. It supports USB 2.0 FS host/function/OTG, dual CAN 2.0B channels (32 mailboxes each), SD host interface (25 MB/s), QSPIX for serial flash fetching, and hardware encryption via TSIP (AES128/192/256, RSA, ECC, TRNG). Used in industrial HMI, smart metering, and secure IoT edge nodes requiring real-time control and tamper-resistant firmware.
For engineers reviewing the R5F5671EDGFB#10 datasheet, R5F5671EDGFB#10 pinout, R5F5671EDGFB#10 application, or R5F5671EDGFB#10 equivalent, key selection considerations include its 145-pin TFLGA (0.65-mm pitch) package, -40°C to +105°C operating range (G-version), 12-bit dual A/D converter (20 total channels), RTC with battery backup, and IEC60730-compliant safety features including oscillation-stop detection and self-diagnostic A/D.
Technical Context
The R5F5671EDGFB#10 implements the RXv3 CPU core with 113 instructions, 16 general-purpose 32-bit registers, and dual-precision FPU supporting 21 double-precision floating-point instructions. Its memory subsystem includes 2-MB code flash with zero-wait access up to 60 MHz (or cache-hit at 120 MHz), 8-KB data flash rated for 100,000 erase/write cycles, and 384-KB SRAM with no wait states at full 120-MHz operation.
Peripheral integration centers on deterministic real-time control: MTU3a (9-channel 16/32-bit timer), TPUa (6-channel 16-bit pulse unit), CMTW (2-channel 32-bit compare match), and ELC (99-event interlinking) enable precise waveform generation and event-driven sequencing. Communication is served by USBb (2 ports), CAN (2 channels), RIICHS (3.4 Mbps), QSPIX, SDHI, and SCIm with 16-byte FIFOs - all clocked independently via PCLKA/PCLKB domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max - delivers 707 CoreMark; supports little/big-endian data and double-precision IEEE-754 FPU with 16×64-bit registers. |
| Memory | 2-MB code flash (dual-bank, BGO programming), 8-KB data flash (100k cycles), 384-KB SRAM (no wait states @120 MHz), 4-KB standby RAM. |
| Timers | MTU3a (9 channels), TPUa (6 channels), CMTW (2×32-bit), TMRb (4×8-bit), IWDTa (14-bit, dedicated 120-kHz oscillator). |
| Analog | Dual 12-bit S12AD units (8+12 channels), 0.48 µs conversion time, self-diagnostic voltage generation, analog input disconnection detection. |
| Security | Trusted Secure IP (TSIP): AES128/192/256, RSA, ECC, SHA256, TRNG, key protection, and IEC60730 compliance functions. |
| I/O & Package | 111 GPIO (5-V tolerant on 20 pins), 145-pin TFLGA (9×9 mm, 0.65-mm pitch), -40°C to +105°C (G-version), VBATT-supported RTC backup. |
| Interfaces | USB 2.0 FS (host/function/OTG), 2×CAN 2.0B (32 mailboxes/channel), QSPIX, SDHI (25 MB/s), RIICHS (3.4 Mbps), SCIm (2×16-byte FIFO), RSCI (Manchester/HBS). |
Pinout & Package
Package: PTlg0145JC-A - 145-pin Thin Fine-Pitch Land Grid Array (TFLGA), 9.0 mm × 9.0 mm body, 0.65 mm pitch, 0.75 mm height, RoHS-compliant, G-version (-40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog power rails (2.7–3.6 V); AVCC0/AVCC1 supply ADC and analog peripherals; decoupling required per datasheet layout guidelines. |
| VBATT | Backup power input | Supplies RTC, sub-clock oscillator, and backup registers during main power loss; enables continuous timekeeping with external coin cell. |
| RES# | Active-low reset input | Asynchronous hardware reset; driven low to force system reset independent of internal voltage monitors or watchdogs. |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; connects to on-chip oscillator circuit for high-accuracy system clock generation. |
| RTCIN/RTCOUT | Sub-clock oscillator terminals | Connects 32.768-kHz crystal for battery-backed RTC; enables calendar/timekeeping and wake-up from deep software standby. |
| USB_DP/USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver supports host/function/OTG without external pull-ups; compliant with USB 2.0 specification at 12 Mbps. |
| TXD0/RXD0 | SCI channel 0 UART signals | Asynchronous serial interface with programmable baud rate; supports LSB/MSB-first, 8–32 bit frames, and start-bit edge/level detection. |
| CTX0/CRX0 | CAN channel 0 differential bus lines | ISO11898-1 compliant physical layer interface; supports standard/extended frames, 32 configurable mailboxes, and loopback self-test. |
| QSPIX_IO0–IO3 | Quad-SPI data lines | Enable quad-SPI, dual-SPI, or standard SPI protocols for direct code/data fetch from external serial flash memory. |
| SD_CLK/SD_CMD/SD_DAT0–3 | SD host interface signals | Support 1-/4-bit SD/SDIO bus at up to 25 MB/s (high-speed mode); includes CRC7/CRC16 error checking and card detection logic. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank code flash | Enables seamless firmware updates: execute from Bank A while programming Bank B as background operation (BGO), eliminating runtime interruption. |
| Event Link Controller (ELC) | Routes 99 internal peripheral events (e.g., timer overflow, ADC completion) directly to other modules without CPU intervention - reduces latency and ISR overhead. |
| Capacitive Touch Sensing Unit (CTSUa) | Supports 17-key self-capacitance or 64-key mutual-capacitance matrix; integrates digital filtering and noise rejection for robust touch detection in noisy industrial environments. |
| IEC60730 Safety Support | Includes hardware-assisted diagnostics: oscillation-stop detection, CRC accelerator (CRCA), IWDTa windowing, A/D self-test, and register write protection - simplifies Class B certification. |
| Independent Watchdog (IWDTa) | Runs on dedicated 120-kHz on-chip oscillator; provides fail-safe reset independent of main clock domain - critical for safety-critical boot and runtime monitoring. |
Applications
| Industrial HMI Panels | Smart Energy Meters |
|---|---|
|
Use Scenario: Touch-enabled front-panel display with real-time energy consumption visualization, tariff switching, and secure firmware updates over USB or SD card. IC Role / Device Role / Timing Role: Main application controller executing RTOS, managing capacitive touch UI, driving LCD via parallel bus, and handling encrypted communication with metrology ICs via SPI/I2C. Use Value: Integrated TSIP enables AES-encrypted firmware signing verification; dual-bank flash allows field-upgradable code without service interruption; RTC with VBATT maintains billing timestamps during power loss. |
Use Scenario: DIN-rail mounted electricity meter with anti-tampering detection, load profiling, and DLMS/COSEM protocol stack execution over PLC or RF mesh. IC Role / Device Role / Timing Role: System-on-chip managing metrology ADC interface, secure crypto operations, CAN-based local network communication, and SDHI-based log storage. Use Value: IEC60730-compliant self-tests (A/D diagnostic, oscillator monitoring) satisfy regulatory requirements; 12-bit dual A/D provides simultaneous voltage/current sampling; CAN 2.0B enables interoperability with legacy grid infrastructure. |
| Secure IoT Edge Gateways | Home Automation Controllers |
|
Use Scenario: Gateway aggregating Zigbee/Z-Wave sensors, running TLS-secured MQTT to cloud, and hosting local rule engine with OTA update capability. IC Role / Device Role / Timing Role: Secure application processor executing Linux Lite or FreeRTOS, performing TLS handshake acceleration via TSIP, and managing USB-hosted cellular modem or Ethernet PHY. Use Value: Hardware TRNG and AES engines offload crypto processing from CPU; QSPIX enables fast boot from external flash; USB OTG supports field technician provisioning via USB stick. |
Use Scenario: Central HVAC/lighting controller with IR remote support, multi-zone temperature sensing, and capacitive touch keypad for local configuration. IC Role / Device Role / Timing Role: Real-time control MCU handling REMCa IR decoding, CTSUa touch interface, 12-bit A/D for thermistor readings, and RSPI-driven display driver. Use Value: REMCa module decodes NEC/RC-5 protocols without CPU polling; CTSUa's mutual-capacitance mode supports 64-key matrix for full QWERTY keypad; integrated temperature sensor calibrates A/D reference drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFP#30 | RX66T Group; 160-MHz CPU, 1-MB flash, no TSIP, no QSPIX, adds 3-phase motor control PWM (MTU3b), fewer CAN channels (1×32 mailbox). | Better suited for servo/inverter drives; lacks hardware crypto and serial flash interface needed for secure OTA updates. | Select when motor control precision outweighs security and external memory needs. |
| R5F572MDHDFB#30 | RX72M Group; 240-MHz CPU, 2-MB flash, TSIP-Lite (no RSA/ECC), added Ethernet MAC, no SDHI, same 145-pin TFLGA footprint. | Targets connected industrial controllers requiring TCP/IP stack; missing SD host limits local firmware/log storage options. | Choose for Ethernet-connected HMIs where network stack performance > local storage flexibility. |
Compared with R5F5671EDGFB#10, the R5F566TEADFP#30 trades security and serial memory support for higher PWM resolution and motor control timing, while the R5F572MDHDFB#30 upgrades CPU speed and adds Ethernet but removes SDHI - making R5F5671EDGFB#10 optimal for secure, locally updatable, sensor-rich edge devices without Ethernet dependency.
Availability
R5F5671EDGFB#10 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, and secure IoT edge node designs requiring stable component supply, long-term lifecycle assurance, and automotive-grade temperature resilience.
Supply support for R5F5671EDGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX671 Group is designed for high-integrity industrial applications demanding real-time responsiveness, functional safety (IEC60730), and hardware-accelerated security - targeting HMI, metering, gateway, and home automation systems where code integrity and peripheral integration are critical.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671EDGFB#10?
The R5F5671EDGFB#10 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark under benchmark conditions. This performance stems from the RXv3 CPU core's optimized instruction set, 16-register bank architecture, and zero-wait-state access to 384-KB SRAM. The R5F5671EDGFB#10 sustains this throughput across mixed workloads including floating-point math, interrupt handling, and peripheral I/O due to its dual-bank flash and ELC-driven event chaining.
Does the R5F5671EDGFB#10 support hardware encryption and IEC60730 compliance?
Yes, the R5F5671EDGFB#10 integrates Trusted Secure IP (TSIP) supporting AES128/192/256, RSA, ECC, SHA256, and a true-random number generator (TRNG), along with dedicated register write protection and A/D self-diagnostic functions. These features, combined with oscillation-stop detection and IWDTa windowing, provide documented IEC60730 Class B compliance - enabling certified safety firmware for industrial control and metering applications using the R5F5671EDGFB#10.
What package type and pin count does the R5F5671EDGFB#10 use?
The R5F5671EDGFB#10 uses a 145-pin Thin Fine-Pitch Land Grid Array (TFLGA) package designated PTlg0145JC-A, measuring 9.0 mm × 9.0 mm with 0.65-mm pitch. It provides 111 GPIOs (20 of which are 5-V tolerant), dedicated USB/SD/CAN/QSPIX signal routing, and thermal pad for enhanced heat dissipation - matching the mechanical and electrical requirements of space-constrained industrial PCBs where the R5F5671EDGFB#10 is deployed.
Can the R5F5671EDGFB#10 execute code directly from external serial flash memory?
Yes, the R5F5671EDGFB#10 supports XIP (execute-in-place) from external serial flash via its QSPIX interface, which implements extended SPI, dual-SPI, and quad-SPI protocols. With address widths configurable from 8 to 32 bits and hardware-accelerated command sequences, the R5F5671EDGFB#10 enables low-latency code fetch - reducing reliance on internal flash and simplifying firmware version management in resource-constrained edge devices.
What are the key differentiators of the R5F5671EDGFB#10 versus other RX600-series MCUs?
The R5F5671EDGFB#10 distinguishes itself within the RX600 family through its combination of 2-MB dual-bank flash, integrated TSIP with full crypto suite (including RSA/ECC), SD host interface (25 MB/s), and QSPIX - features absent in RX65x or RX66T variants. Unlike the RX72M, it retains SDHI while offering identical 145-pin footprint compatibility. These capabilities make the R5F5671EDGFB#10 uniquely suited for secure, locally updatable, sensor-rich industrial edge nodes where the R5F5671EDGFB#10 serves as both controller and trust anchor.
R5F5671EDGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 113
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EDGFB#10 FAQ
1.How can I place an order for R5F5671EDGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EDGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EDGFB#10 reliable?
The price and inventory of R5F5671EDGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EDGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F5671EDGFB#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671EDGFB#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671EDGFB#10?
R5F5671EDGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671EDGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EDGFB#10?
For technical support, including R5F5671EDGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EDGFB#10 requirements.
6.How does Aetrix verify that R5F5671EDGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F5671EDGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EDGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F5671EDGFB#10?
All R5F5671EDGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EDGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EDGFB#10 part is unused and in its original packaging.
Return procedure for R5F5671EDGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5671EDGFB#10 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
