My Inquiry
My Account
Renesas R5F5671EDGFB#30
- Part No.:
- R5F5671EDGFB#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5671EDGFB#30.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:180
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5671EDGFB#30 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control and secure firmware updates.
For engineers reviewing the R5F5671EDGFB#30 datasheet, R5F5671EDGFB#30 pinout, R5F5671EDGFB#30 application, or R5F5671EDGFB#30 equivalent, this page delivers verified specifications, package mapping to PLQP0144KA-B (144-pin LQFP), functional pin roles, IEC60730-compliant safety features, and two validated alternative MCUs for migration planning.
Technical Context
The R5F5671EDGFB#30 implements the RXv3 CPU core with 113 instructions, 16 general-purpose 32-bit registers, and dual-precision floating-point coprocessor supporting 21 FP64 instructions. It integrates a memory protection unit (MPU) with eight configurable regions and supports little-endian or big-endian data arrangement.
Its clock system combines external crystal (8–24 MHz), sub-clock (32.768 kHz), and internal oscillators (LOCO/HOCO/IWDT-dedicated), with independent frequency domains: ICLK up to 120 MHz for CPU/QSPIX, PCLKA up to 120 MHz for MTU/RSPI/RIICHS, and PCLKB up to 60 MHz for most peripherals including S12AD units.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark score - enables deterministic real-time task scheduling in motor control and protocol stacks. |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k erase cycles), 384 KB SRAM (no wait states) - supports secure OTA updates and large buffer handling. |
| FPU | IEEE-754 double-precision coprocessor - accelerates sensor fusion, digital power control, and cryptographic key generation without software emulation. |
| Peripherals | 2× CAN FD-capable channels (32 mailboxes), 1× USB 2.0 FS host/function, 1× SDHI (25 MB/s), 1× QSPIX (quad-SPI fetch), 2× 12-bit S12AD (8+12 ch) - consolidates connectivity and analog acquisition in single-chip designs. |
| Security | Trusted Secure IP (TSIP) with AES128/192/256, RSA, ECC, TRNG, SHA256, and key protection - meets IEC60730 Class B and IoT device attestation requirements. |
| Package & Temp | PLQP0144KA-B (144-pin LQFP, 20 × 20 mm, 0.5 mm pitch), –40°C to +85°C (D-version) - compatible with standard PCB assembly and industrial thermal environments. |
| Power | 2.7–3.6 V supply, four low-power modes (deep software standby with 4 KB backup RAM), VBATT-supported RTC - enables battery-backed operation in energy-metering applications. |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package (20 × 20 mm, 0.50-mm pitch), RoHS-compliant, lead-free, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Core & analog power supply | Must be decoupled individually; AVCC0/AVCC1 power ADC/S12AD units and require separate 100 nF + 10 µF filtering for 12-bit accuracy. |
| VBATT | Backup power input | Supplies RTC, backup registers, and sub-clock oscillator during main power loss - requires 1.8–3.6 V battery or supercapacitor. |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz parallel-resonant crystals; essential for USB timing compliance and high-accuracy system clock generation. |
| RES# | Active-low reset input | Asynchronous hardware reset; must be held low ≥100 ns after VCC stabilization to ensure reliable initialization. |
| USB_DP/USB_DM | USB 2.0 full-speed differential pair | Direct connection to USB connector; no external termination resistors required - simplifies layout and reduces BOM count. |
| SD0_CLK/SD0_CMD/SD0_DAT[0:3] | SD host interface signals | Support 1-/4-bit SD/SDIO bus; enable direct interfacing with SD cards and Wi-Fi/BLE modules compliant with SD Physical Layer v3.01. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed via background operation (BGO), eliminating runtime interruption. |
| Event Link Controller (ELC) | Hardware-triggered peripheral chaining (e.g., TPU output → A/D start → DMA transfer) reduces CPU overhead and improves deterministic latency. |
| Capacitive Touch Sensing Unit (CTSUa) | Supports 17 self-capacitance keys or 64 mutual-capacitance keys with built-in noise rejection - eliminates need for external touch controller in HMI designs. |
| IEC60730 safety functions | Includes oscillation-stop detection, CRC-accelerated memory checks, IWDT windowing, and A/D self-diagnostic - simplifies Class B certification evidence collection. |
| Trusted Memory (TM) protection | Prevents unauthorized readout of code stored in designated flash areas - enforces secure boot and protects proprietary algorithms from reverse engineering. |
Applications
| Industrial HMI Panel | Smart Energy Meter |
|---|---|
|
Use Scenario: Touch-enabled display with real-time energy monitoring, tariff switching, and tamper detection. IC Role / Device Role / Timing Role: Main application MCU managing CTSU touch input, SDHI for log storage, CAN for utility communication, and RTC for time-stamped events. Use Value: Integrated QSPIX enables fast boot from serial flash; TSIP secures firmware updates; 120 MHz CPU handles GUI rendering and protocol parsing concurrently. |
Use Scenario: DIN-rail mounted meter with voltage/current sensing, PLC/G3-PLC backhaul, and local LCD display. IC Role / Device Role / Timing Role: System controller executing metrology algorithms, managing isolated RS485/CAN interfaces, and maintaining secure timekeeping via VBATT-backed RTC. Use Value: Dual 12-bit S12AD units acquire analog inputs simultaneously; ELC synchronizes sampling with PWM-driven isolation drivers; low-power modes extend battery life during outage. |
| Home Automation Gateway | Motor Control Drive |
|
Use Scenario: Multi-protocol hub connecting Zigbee, BLE, and KNX devices to cloud via Ethernet/Wi-Fi (via SDIO). IC Role / Device Role / Timing Role: Protocol translation engine using USB host for dongles, RIICHS for sensor I²C buses, and RSCI for LIN-based actuators. Use Value: 13-channel SCI support enables concurrent UART-based device management; TSIP encrypts local credentials before SDIO upload to cloud endpoint. |
Use Scenario: Brushless DC motor drive with field-oriented control (FOC), current sensing, and overtemperature protection. IC Role / Device Role / Timing Role: Real-time motion controller generating complementary PWM via MTU3a, sampling ADCs at precise intervals, and executing FOC loop in <1 µs. Use Value: RXv3 FPU computes trigonometric functions natively; POE3a prevents shoot-through in gate drivers; temperature sensor feeds thermal derating logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EDGFB#30 | Same RXv3 core, 120 MHz, but 1 MB flash, 256 KB SRAM, and reduced peripheral set (no SDHI, only 1 CAN channel, no QSPIX). | Suitable for cost-sensitive motor control or sensor nodes where SD card logging and quad-SPI boot are unnecessary. | Select when BOM cost reduction is prioritized over future firmware scalability and multi-interface consolidation. |
| R5F566TEADFP#30 | RX66T group, 160 MHz, optimized for motor control with 32-bit MTU3b, 3-phase PWM timers, and enhanced analog front-end - lacks TSIP, SDHI, and USB. | Targeted at high-performance inverters and servo drives requiring >100 kHz PWM resolution and fast current-loop response. | Choose for dedicated motor control where security and host connectivity are secondary to PWM precision and ADC synchronization. |
Compared with R5F5671EDGFB#30, R5F5670EDGFB#30 trades flash/SRAM capacity and interface breadth for lower unit cost, while R5F566TEADFP#30 shifts focus to deterministic PWM timing and analog acquisition - making the R5F5671EDGFB#30 optimal for applications demanding balanced compute, security, and heterogeneous connectivity.
Availability
R5F5671EDGFB#30 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, home automation gateways, and motor control drives requiring stable component supply across multi-year production cycles.
Supply support for R5F5671EDGFB#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX671 Group is designed for high-integrity industrial applications requiring real-time performance, functional safety (IEC60730), and secure firmware execution - targeting smart infrastructure, energy management, and human-machine interface systems.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671EDGFB#30?
The R5F5671EDGFB#30 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark points under benchmark conditions. This performance stems from the RXv3 CPU core's efficient instruction pipeline and dual-bank flash architecture enabling zero-wait-state execution at 60 MHz and one-wait-state access at full speed. The R5F5671EDGFB#30 sustains deterministic real-time behavior critical for industrial control loops and protocol stacks.
Does the R5F5671EDGFB#30 support secure firmware updates and cryptographic operations?
Yes, the R5F5671EDGFB#30 integrates Trusted Secure IP (TSIP) with hardware-accelerated AES128/192/256, RSA, ECC, SHA256, and a true-random number generator (TRNG). It supports secure boot via Trusted Memory (TM) protection and enables authenticated, encrypted firmware updates - meeting IEC60730 Class B requirements. These capabilities are intrinsic to the R5F5671EDGFB#30 silicon and do not rely on external co-processors.
What package type and pin count does the R5F5671EDGFB#30 use?
The R5F5671EDGFB#30 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package measuring 20 × 20 mm with 0.50-mm pitch. This RoHS-compliant, lead-free LQFP variant supports standard surface-mount assembly and provides 111 general-purpose I/O pins with 5-V tolerance on 20 pins. The R5F5671EDGFB#30's pinout is fully documented in Renesas document R01DS0373EJ0120.
Which communication interfaces are integrated into the R5F5671EDGFB#30?
The R5F5671EDGFB#30 integrates CAN (2 channels, 32 mailboxes each), USB 2.0 Full-Speed host/function/OTG, SD host interface (SDHI), Quad-SPI (QSPIX), three I²C interfaces (RIIC/RIICHS), 13 serial channels (SCIk/SCIm/SCIh), two RSCI with Manchester encoding, and SPI variants (RSPId/RSPIA). This comprehensive suite enables direct connectivity to sensors, displays, wireless modules, and industrial networks without external bridge ICs - a defining capability of the R5F5671EDGFB#30.
How does the R5F5671EDGFB#30 handle low-power operation and battery backup?
The R5F5671EDGFB#30 supports four low-power modes - Sleep, All-module Clock Stop, Software Standby, and Deep Software Standby - with typical current draw as low as 0.5 µA in deep standby. Its VBATT pin powers the RTC, backup registers, and sub-clock oscillator during main supply loss, preserving timekeeping and state across power interruptions. This functionality is implemented directly in the R5F5671EDGFB#30 die and requires no external supervisor circuitry.
R5F5671EDGFB#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 113
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EDGFB#30 FAQ
1.How can I place an order for R5F5671EDGFB#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EDGFB#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EDGFB#30 reliable?
The price and inventory of R5F5671EDGFB#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EDGFB#30 is usually 5 days.
3.What payment methods are accepted for R5F5671EDGFB#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671EDGFB#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671EDGFB#30?
R5F5671EDGFB#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671EDGFB#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EDGFB#30?
For technical support, including R5F5671EDGFB#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EDGFB#30 requirements.
6.How does Aetrix verify that R5F5671EDGFB#30 is sourced from the original manufacturer or authorized distributors?
All R5F5671EDGFB#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EDGFB#30 meets industry standards.
7.What is the process for return or replacement of R5F5671EDGFB#30?
All R5F5671EDGFB#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EDGFB#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EDGFB#30 part is unused and in its original packaging.
Return procedure for R5F5671EDGFB#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5671EDGFB#30 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
