Renesas R5F5671EDGFM#30
- Part No.:
- R5F5671EDGFM#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
R5F5671EDGFM#30.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:317
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5671EDGFM#30 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control and secure firmware updates.
For engineers reviewing the R5F5671EDGFM#30 datasheet, R5F5671EDGFM#30 pinout, R5F5671EDGFM#30 application, or R5F5671EDGFM#30 equivalent, key selection criteria include its 120-MHz RXv3 core performance (707 CoreMark), TSIP-based AES256/SHA256 encryption, 114 GPIOs with 5-V tolerance, and IEC60730-compliant safety features including self-diagnostic A/D and oscillation-stop detection.
Technical Context
The R5F5671EDGFM#30 implements the RXv3 CPU core with 16×32-bit general-purpose registers, double-precision FPU (16×64-bit data registers), and collective register bank save for fast context switching. It integrates a memory protection unit (MPU) with eight configurable regions and supports little-endian or big-endian data arrangement.
Its clock system combines external crystal (8–24 MHz), sub-clock (32.768 kHz), and internal oscillators (LOCO/HOCO/IWDT-dedicated), enabling independent domain clocks: ICLK up to 120 MHz for CPU/QSPIX, PCLKA up to 120 MHz for MTU/RSPI, and PCLKB up to 60 MHz for most peripherals including S12AD units.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max - delivers 707 CoreMark; supports double-precision IEEE-754 FPU and collective register bank save for deterministic RTOS context switches. |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k write cycles), 384 KB SRAM (no-wait at 120 MHz), 4 KB standby RAM - enables secure firmware updates and deep-sleep RTC retention. |
| Security | Trusted Secure IP (TSIP) with AES128/192/256, RSA, ECC, SHA256, TRNG, and key-protection logic - meets IEC60730 Class B requirements for encrypted boot and runtime integrity. |
| Peripherals | 2× CAN (ISO11898-1, 32 mailboxes/channel), 1× USB 2.0 FS host/function/OTG, 1× SDHI (25 MB/s), 1× QSPIX (quad-SPI fetch), 2× 12-bit S12AD (8+12 ch), CTSU (17-key self-capacitance) - supports motor control + connectivity + HMI in single chip. |
| Power & Temp | 2.7–3.6 V supply, four low-power modes (deep software standby), –40°C to +105°C (G-version), VBATT backup for RTC/backup registers - suitable for unregulated industrial power rails and extended ambient operation. |
| Package & Pins | PLQP0144KA-B (144-pin LFQFP, 20×20 mm, 0.5 mm pitch), 114 GPIOs with 5-V tolerance, open-drain, pull-up - provides robust I/O for mixed-signal industrial PCB layouts. |
Pinout & Package
Package: PLQP0144KA-B - 144-pin Low-profile Quad Flat Package, 20 mm × 20 mm body, 0.50 mm pitch, exposed thermal pad, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains for digital logic and ADC reference; decoupling required per datasheet layout guidelines. |
| VBATT | Backup power input | Supplies RTC, sub-clock oscillator, and backup registers during main power loss - enables timekeeping without external supercap. |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal; internal PLL generates 120 MHz ICLK - critical for USB timing and high-speed peripheral synchronization. |
| RES# | Active-low reset input | Asynchronous hardware reset; internal POR/LVD ensures reliable startup under brownout conditions - no external reset IC needed. |
| USB_DP / USB_DM | Full-speed USB 2.0 differential pair | Integrated transceiver eliminates external PHY; supports host/function/OTG with 2 KB on-chip buffer - reduces BOM for embedded USB devices. |
| SD_CLK / SD_CMD / SD_DAT0–3 | SD host interface signals | Direct 4-bit SD bus interface compliant with SD Physical Layer Spec v3.01 - enables local firmware storage and field updates via removable media. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: one bank executes while the other is reprogrammed via background operation (BGO), eliminating runtime interruption. |
| IEC60730-compliant safety suite | Includes oscillation-stop detection, CRC-A for flash, self-diagnostic A/D, IWDT windowing, and register write protection - certified for Class B functional safety without external monitors. |
| Capacitive touch sensing (CTSU) | Supports 17-key self-capacitance or 64-key mutual-capacitance matrix with built-in noise rejection - replaces mechanical buttons in harsh industrial environments. |
| Event Link Controller (ELC) | Hardware interconnect for 99 internal events (e.g., timer overflow → A/D trigger → DMA transfer) - offloads CPU, reduces latency, and improves deterministic response. |
| Trusted Memory (TM) function | Restricts code execution to protected TM target area and prevents read-out of sensitive firmware - enforces secure boot and intellectual property protection. |
Applications
| Industrial HMI Panel | Smart Energy Meter |
|---|---|
|
Use Scenario: Touch-enabled front-panel display with real-time energy monitoring, tariff switching, and tamper detection. IC Role / Device Role / Timing Role: Main application MCU handling GUI rendering, capacitive touch decoding, SDHI-based log storage, and secure OTA updates via TSIP-encrypted firmware. Use Value: Integrated CTSU eliminates external touch controller; dual-bank flash enables fail-safe field updates; 120 MHz core processes multi-threaded UI and metering algorithms concurrently. |
Use Scenario: DIN-rail mounted electricity meter with pulse counting, communication via CAN/USB, and cryptographic billing data signing. IC Role / Device Role / Timing Role: System-on-chip managing metrology sampling (S12AD), CAN bus data aggregation, USB configuration interface, and AES256-signed data export. Use Value: On-chip CAN and USB reduce external transceivers; TSIP accelerates ECDSA signing; temperature sensor compensates metrology drift across –40°C to +105°C range. |
| Factory Automation Gateway | Home Appliance Controller |
|
Use Scenario: Edge gateway aggregating Modbus RTU sensors over RSPI/SCI and forwarding to cloud via USB-connected cellular modem. IC Role / Device Role / Timing Role: Protocol translation hub using multiple SCI/RSPI channels, USB device mode for modem tethering, and SDHI for local event buffering. Use Value: 13-channel SCI support enables concurrent legacy serial protocols; QSPIX boots from external flash; ELC synchronizes sensor polling with DMA transfers. |
Use Scenario: Washing machine main controller with motor drive (PWM via MTU3a), water level sensing (A/D), and remote diagnostics via USB. IC Role / Device Role / Timing Role: Real-time motor control MCU generating complementary PWM with dead-time insertion, reading analog pressure/temperature, and logging faults to SD card. Use Value: MTU3a's complementary PWM and POE3a prevent shoot-through in inverter drives; 12-bit A/D achieves ±0.1% measurement accuracy; standby RAM retains error logs during power loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEADFP#30 | Same RXv3 core, 100-pin LQFP, 1 MB flash, 256 KB SRAM, no SDHI or QSPIX - lacks serial memory fetch and SD card interface. | Suitable for cost-sensitive motor control where external flash/SD is unnecessary; insufficient for OTA update storage or media playback. | Select when footprint and BOM cost are prioritized over connectivity and local firmware storage capability. |
| R5F572MDHDFP#30 | RX72M series, 240 MHz, 2 MB flash, 1 MB SRAM, Ethernet MAC, but no CTSU or TSIP - adds networking, removes touch and crypto acceleration. | Better for networked PLCs or gateways needing TCP/IP stack; unsuitable for touch UI or secure boot-critical applications. | Choose for Ethernet-connected edge controllers; avoid when capacitive touch or hardware AES is mandatory. |
Compared with R5F5671EDGFM#30, the R5F566TEADFP#30 reduces memory and peripheral count for lower-cost implementations, while the R5F572MDHDFP#30 trades touch/crypto for Ethernet - making R5F5671EDGFM#30 uniquely balanced for secure, connected, touch-enabled industrial endpoints.
Availability
R5F5671EDGFM#30 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, factory automation gateways, and home appliance controllers requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for R5F5671EDGFM#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX671 Group is designed for high-integrity industrial applications demanding real-time performance, functional safety (IEC60730), and secure connectivity - targeting smart meters, programmable logic controllers, and human-machine interfaces.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671EDGFM#30?
The R5F5671EDGFM#30 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark under benchmark conditions. This performance stems from its RXv3 CPU core with optimized pipeline, double-precision FPU, and zero-wait-state access to 384 KB SRAM - enabling deterministic real-time task execution in industrial control loops.
Does the R5F5671EDGFM#30 support secure firmware updates and cryptographic operations?
Yes, the R5F5671EDGFM#30 integrates Trusted Secure IP (TSIP) supporting AES128/192/256, SHA256, RSA, ECC, and a true random number generator. Its dual-bank flash allows background programming while executing from the active bank, and Trusted Memory (TM) prevents unauthorized code readout - together enabling secure, fail-safe OTA updates.
What package type and pin count does the R5F5671EDGFM#30 use?
The R5F5671EDGFM#30 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package with 20 mm × 20 mm body size and 0.50 mm pitch. It provides 114 general-purpose I/O pins, 20 of which are 5-V tolerant - ideal for industrial PCBs interfacing with legacy 5-V sensors and logic.
Which communication interfaces are integrated into the R5F5671EDGFM#30?
The R5F5671EDGFM#30 integrates CAN (2 channels, ISO11898-1), USB 2.0 Full-Speed host/function/OTG, SD host interface (SDHI), Quad-SPI (QSPIX), 13-channel SCI, 2-channel RSCI, 3-channel RSPId, 1-channel RSPIA, 3-channel RIIC, and 1-channel RIICHS - covering fieldbus, removable media, serial flash, and high-speed I²C in a single device.
How does the R5F5671EDGFM#30 meet IEC60730 Class B safety requirements?
The R5F5671EDGFM#30 meets IEC60730 Class B through integrated hardware safety features: oscillation-stop detection, CRC-A for flash integrity, self-diagnostic A/D converter, windowed independent watchdog timer (IWDTa), memory protection unit (MPU), and register write protection - all documented in Renesas' IEC60730 compliance report for the RX671 Group.
R5F5671EDGFM#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 44
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 10x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EDGFM#30 FAQ
1.How can I place an order for R5F5671EDGFM#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EDGFM#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EDGFM#30 reliable?
The price and inventory of R5F5671EDGFM#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EDGFM#30 is usually 5 days.
3.What payment methods are accepted for R5F5671EDGFM#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671EDGFM#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671EDGFM#30?
R5F5671EDGFM#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671EDGFM#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EDGFM#30?
For technical support, including R5F5671EDGFM#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EDGFM#30 requirements.
6.How does Aetrix verify that R5F5671EDGFM#30 is sourced from the original manufacturer or authorized distributors?
All R5F5671EDGFM#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EDGFM#30 meets industry standards.
7.What is the process for return or replacement of R5F5671EDGFM#30?
All R5F5671EDGFM#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EDGFM#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EDGFM#30 part is unused and in its original packaging.
Return procedure for R5F5671EDGFM#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5671EDGFM#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

