Renesas R5F5671EDGFP#30
- Part No.:
- R5F5671EDGFP#30
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F5671EDGFP#30.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:180
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5671EDGFP#30 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI, smart metering, and secure IoT edge nodes.
For engineers reviewing the R5F5671EDGFP#30 datasheet, R5F5671EDGFP#30 pinout, R5F5671EDGFP#30 application, or R5F5671EDGFP#30 equivalent, key selection criteria include its 144-pin LFQFP package (PLQP0144KA-B), -40°C to +85°C D-grade temperature range, TSIP-based AES256/SHA256 encryption, 12-bit dual A/D converter with self-diagnostic capability, and IEC60730-compliant safety features for functional safety-critical firmware.
Technical Context
The R5F5671EDGFP#30 implements the RXv3 CPU core with collective register bank save, memory protection unit (MPU), and JTAG/FINE debug interfaces. It integrates dual-bank flash enabling background programming and safe firmware updates, alongside 8 KB data flash rated for 100,000 erase/write cycles.
Clock architecture includes PLL-driven 120 MHz system clock (ICLK), independent PCLKA/PCLKB domains (up to 120 MHz/60 MHz), sub-clock oscillator for RTC backup, and dedicated 120 kHz IWDT oscillator. Peripheral timing is strictly partitioned: MTU3a/RSPI/SCIm run on PCLKA; S12AD units synchronize to PCLKC/PCLKD (60 MHz); QSPIX runs at full ICLK speed.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark score - enables real-time deterministic control with floating-point math acceleration. |
| Memory | 2 MB code flash (dual-bank), 8 KB data flash (100k cycles), 384 KB SRAM (no wait states), 4 KB standby RAM - supports robust firmware update, logging, and low-power retention. |
| Analog Peripherals | Dual 12-bit S12AD (8+12 ch), ±1°C on-die temperature sensor, self-diagnostic A/D - meets IEC60730 Class B requirements for analog subsystem validation. |
| Security | Trusted Secure IP (TSIP) with AES128/192/256, SHA256, RSA, ECC, TRNG, and key protection - provides hardware-rooted trust for secure boot and OTA updates. |
| Connectivity | CAN v2.0B (2 ch, 32 mailboxes), USB 2.0 FS host/function/OTG, SDHI (25 MB/s), QSPIX (fetch from serial flash), RIICHS (3.4 Mbps) - enables mixed-protocol industrial gateway design. |
| Package & Temp | PLQP0144KA-B: 144-pin LFQFP, 20 × 20 mm, 0.50 mm pitch, D-grade (–40°C to +85°C) - standard surface-mount footprint compatible with automated assembly. |
Pinout & Package
PLQP0144KA-B is a 144-pin Low-profile Quad Flat Package (LFQFP) with 0.50 mm pitch, 20 × 20 mm body size, and exposed thermal pad. Pin assignment follows Renesas' standardized RX671 Group pinout for 144-pin variants, supporting full peripheral mapping including 111 general-purpose I/O pins (20 with 5-V tolerance), dual CAN transceiver pins, USB D+/D−, SDIO bus, QSPIX signals, and CTSU electrode inputs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | Separate 2.7–3.6 V domains enable noise isolation between digital logic and ADC/RTC circuits. |
| VBATT | Backup power input | Supplies RTC, backup registers, and sub-clock oscillator during main power loss - critical for timekeeping in energy meters. |
| XTAL / EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator for precise system clock generation and USB timing compliance. |
| USB_DP / USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates external PHY; supports host, device, and OTG modes without pull-up resistors. |
| SD_CLK / SD_CMD / SD_DAT0–3 | SD host interface signals | Direct connection to SD memory/SDIO cards; supports high-speed mode (25 MB/s) and 1-/4-bit bus widths. |
| QSPIX_IO0–3 / QSPIX_SCK / QSPIX_SSL | Quad-SPI memory interface | Enables XIP (execute-in-place) from external serial flash - reduces boot time and external memory footprint. |
| CTSU_AD0–16 | Capacitive touch sensing electrodes | Self- and mutual-capacitance support up to 64 keys; no external RC components required for basic touch button implementation. |
Key Features
| Feature | Design Value |
|---|---|
| IEC60730 Safety Support | Oscillation-stop detection, CRC-A for memory, IWDT windowing, A/D self-test, and register write protection - simplifies Class B certification for home appliance and industrial controls. |
| Dual-Bank Flash Architecture | Enables seamless firmware updates: new image programmed into inactive bank while active bank executes - zero downtime field upgrades. |
| Event Link Controller (ELC) | 99 internal event signals routed without CPU intervention - e.g., TPU timer overflow triggers A/D conversion or GPIO toggle, reducing ISR latency and CPU load. |
| Low-Power Modes | Four modes (Sleep, All-module stop, Software standby, Deep software standby) with VBATT-backed RTC - extends battery life in portable and remote monitoring devices. |
| Secure Boot & Key Management | TSIP enforces encrypted firmware decryption and signature verification at boot; prevents unauthorized code execution and key extraction via side-channel attacks. |
Applications
| Industrial HMI Panel | Smart Electricity Meter |
|---|---|
Use Scenario: Touch-enabled local operator interface for PLC-controlled machinery with real-time status display and parameter adjustment. IC Role / Device Role / Timing Role: Main application processor handling GUI rendering, CTSU touch decoding, CAN bus communication with controllers, and USB firmware updates. Use Value: Integrated 12-bit A/D reads panel voltage/current sensors; dual-bank flash allows safe field updates without halting machine operation. | Use Scenario: Revenue-grade meter measuring grid voltage, current, and power factor with tamper detection and secure data logging. IC Role / Device Role / Timing Role: System-on-chip managing metrology ADC interface, RTC time stamping, AES-encrypted data storage in data flash, and DLMS/COSEM over PLC or RF module. Use Value: TSIP accelerates SHA256 signatures for firmware integrity; VBATT-backed RTC ensures accurate billing timestamps during mains outage. |
| Secure IoT Gateway | Home Appliance Controller |
Use Scenario: Edge node aggregating sensor data from BLE/Zigbee sub-devices, performing local analytics, and forwarding to cloud via Ethernet/Wi-Fi bridge. IC Role / Device Role / Timing Role: Central MCU running RTOS, managing multiple serial interfaces (SCI, RSPI, RIIC), encrypting payloads with TSIP, and scheduling low-power wake-ups. Use Value: QSPIX fetches application code from external flash; SDHI hosts local log files; CAN/USB provide service port access for diagnostics. | Use Scenario: Washing machine main controller coordinating motor drive, water valve actuation, temperature sensing, and user interface. IC Role / Device Role / Timing Role: Functional safety MCU executing IEC60730-compliant motor control loops, monitoring door lock status, and validating sensor inputs via A/D self-test. Use Value: MPU isolates safety-critical tasks; IWDT windowing prevents runaway code; CTSU replaces mechanical buttons with waterproof touch interface. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EDGFP#30 | Same RXv3 core, 120 MHz, but 1 MB code flash, 256 KB SRAM, no SDHI or QSPIX - lacks serial memory fetch and SD card support. | Suitable for cost-sensitive HMI or motor control where external flash or SD storage is unnecessary. | Select when firmware size < 1 MB and no local mass storage or XIP from serial flash is required. |
| R5F566TEADFP#30 | RX66T Group part: optimized for motor control with 32-bit MTU3 timers, 3-phase PWM, and encoder interfaces - no TSIP, no SDHI, no CTSU. | Targeted at inverter drives and servo systems requiring high-precision PWM and position feedback - not suitable for secure or touch-enabled applications. | Choose only for dedicated motor control; lacks security, touch, and storage peripherals present in R5F5671EDGFP#30. |
Compared with R5F5670EDGFP#30, the R5F5671EDGFP#30 adds SDHI, QSPIX, and 1 MB more flash for local data logging and firmware flexibility; versus R5F566TEADFP#30, it trades motor-specific timers for broad connectivity and security - making it optimal for connected, certified, and user-interface-rich industrial endpoints.
Availability
R5F5671EDGFP#30 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, secure IoT gateways, and home appliance controllers requiring stable component supply across multi-year production cycles.
Supply support for R5F5671EDGFP#30 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Japan, delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise applications.
The RX671 Group is designed for secure, connected, and safety-certifiable industrial edge devices - integrating TSIP cryptography, IEC60730 compliance features, and rich connectivity to replace discrete security + MCU + interface IC combinations.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671EDGFP#30?
The R5F5671EDGFP#30 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark in benchmark testing. This performance stems from the RXv3 CPU core's efficient instruction pipeline, double-precision FPU, and zero-wait-state access to 384 KB SRAM. The R5F5671EDGFP#30 delivers deterministic real-time response for control algorithms while maintaining low power consumption in active mode.
Does the R5F5671EDGFP#30 support secure boot and cryptographic operations?
Yes, the R5F5671EDGFP#30 integrates Trusted Secure IP (TSIP) supporting AES128/192/256, SHA256, RSA, ECC, and a true random number generator. It enables hardware-accelerated secure boot, encrypted firmware updates, and runtime key protection. These capabilities are fully implemented in the R5F5671EDGFP#30 silicon and require no external security co-processor - meeting foundational requirements for PSA Level 1 and IEC60730 Class B certification.
What package type and pin count does the R5F5671EDGFP#30 use?
The R5F5671EDGFP#30 uses the PLQP0144KA-B package: a 144-pin Low-profile Quad Flat Package with 0.50 mm pitch and 20 × 20 mm body size. It provides 111 general-purpose I/O pins (20 with 5-V tolerance), dedicated USB, CAN, SDIO, QSPIX, and CTSU signal routing. This package is RoHS-compliant and qualified for reflow soldering per J-STD-020.
Can the R5F5671EDGFP#30 execute code directly from external serial flash memory?
Yes, the R5F5671EDGFP#30 supports execute-in-place (XIP) from external serial flash via its QSPIX interface. The QSPIX controller handles extended SPI, dual-SPI, and quad-SPI protocols with configurable address width (8–32 bits), enabling fast, low-pin-count memory expansion. This capability is natively supported in the R5F5671EDGFP#30 without external glue logic or address translation - reducing BOM cost and PCB area.
What safety certifications and built-in features does the R5F5671EDGFP#30 support for IEC60730 compliance?
The R5F5671EDGFP#30 includes dedicated hardware features for IEC60730 Class B compliance: oscillation-stop detection, CRC-A for flash memory, windowed independent watchdog timer (IWDTa), A/D converter self-diagnostic function, and register write protection. These are implemented in silicon and documented in Renesas' IEC60730 safety manual for the RX671 Group - enabling streamlined qualification of end equipment using the R5F5671EDGFP#30 as the safety MCU.
R5F5671EDGFP#30 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, UART/USART, USB
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 80
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EDGFP#30 FAQ
1.How can I place an order for R5F5671EDGFP#30 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EDGFP#30 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EDGFP#30 reliable?
The price and inventory of R5F5671EDGFP#30 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EDGFP#30 is usually 5 days.
3.What payment methods are accepted for R5F5671EDGFP#30?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671EDGFP#30 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671EDGFP#30?
R5F5671EDGFP#30 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671EDGFP#30 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EDGFP#30?
For technical support, including R5F5671EDGFP#30 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EDGFP#30 requirements.
6.How does Aetrix verify that R5F5671EDGFP#30 is sourced from the original manufacturer or authorized distributors?
All R5F5671EDGFP#30 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EDGFP#30 meets industry standards.
7.What is the process for return or replacement of R5F5671EDGFP#30?
All R5F5671EDGFP#30 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EDGFP#30, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EDGFP#30 part is unused and in its original packaging.
Return procedure for R5F5671EDGFP#30:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5671EDGFP#30 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

