Renesas R5F5671EDGLJ#20
- Part No.:
- R5F5671EDGLJ#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-TFLGA
- Datasheet:
-
R5F5671EDGLJ#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 100TFLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F5671EDGLJ#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 1 MB on-chip code flash, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI and smart metering systems requiring real-time control and secure firmware execution.
For engineers reviewing the R5F5671EDGLJ#20 datasheet, R5F5671EDGLJ#20 pinout, R5F5671EDGLJ#20 application, or R5F5671EDGLJ#20 equivalent, key selection criteria include its 120-MHz RXv3 core performance (707 CoreMark), dual-bank flash for safe firmware updates, TSIP-based AES256/SHA256 encryption, and 114 GPIO with 5-V tolerance - all within a 144-pin LFQFP package rated for –40°C to +105°C operation.
Technical Context
The R5F5671EDGLJ#20 implements the RXv3 CPU core with hardware support for double-precision floating-point arithmetic, memory protection unit (MPU), and collective register bank save - enabling deterministic real-time task switching and IEC60730-compliant functional safety. Its clock system integrates PLL, sub-clock oscillator (32.768 kHz), and dedicated IWDT oscillator (120 kHz) for independent watchdog timing.
Peripheral integration includes two CAN channels (32 mailboxes each), USB 2.0 FS host/function with 2 KB buffer, SDHI supporting 25 MB/s high-speed mode, and QSPIX for serial flash boot - all synchronized to configurable PCLK domains (PCLKA up to 120 MHz, PCLKB up to 60 MHz) to balance performance and power efficiency across subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max - delivers 707 CoreMark; supports double-precision FPU per IEEE-754. |
| Memory | 1 MB code flash (dual-bank), 8 KB data flash (100k write cycles), 384 KB SRAM (no wait states). |
| Operating Temp | –40°C to +105°C (G-version) - qualified for extended industrial environments. |
| Package | PLQP0144KA-B: 144-pin LFQFP, 20 × 20 mm, 0.50-mm pitch - compatible with standard reflow profiles. |
| Security | Trusted Secure IP (TSIP): AES128/192/256, SHA256, TRNG, key protection - enables secure boot and OTA updates. |
| Peripherals | 2× CAN, 1× USB 2.0 FS, 1× SDHI (25 MB/s), 1× QSPIX, 2× 12-bit ADC (8+12 ch), CTSU (17-key self-capacitance). |
| Power | 2.7–3.6 V supply; four low-power modes including deep software standby with 4 KB backup RAM. |
Pinout & Package
PLQP0144KA-B is a 144-pin Low-profile Quad Flat Package (LFQFP) with 0.50-mm pitch, 20 × 20 mm body size, and exposed thermal pad - designed for industrial PCB layouts requiring thermal reliability and manual rework compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Main & analog power supply | 2.7–3.6 V input; separate analog domains ensure ADC accuracy and noise immunity. |
| VBATT | Backup power input | Enables RTC and backup registers during main power loss - critical for time-stamped event logging. |
| RES# | Active-low reset input | Hardware reset assertion; synchronous release ensures deterministic startup sequence. |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external resonator - primary clock source for 120 MHz PLL operation. |
| USB_DP/USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates external PHY; supports host, function, and OTG roles. |
| SD0_CMD, SD0_CLK, SD0_DAT[0:3] | SD host interface signals | Direct connection to SD/SDIO cards; supports 4-bit bus mode at 25 MB/s - no external level shifters required. |
| TXD0/RXD0 | SCI channel 0 UART interface | Asynchronous serial communication; configurable baud rate generator enables robust RS-485 interfacing. |
| CTSU_SOU0–CTSU_SOU16 | Capacitive touch sense outputs | Drive self-capacitance electrodes; supports up to 17 independent touch keys with built-in noise filtering. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables background programming and seamless firmware update without halting application execution. |
| Trusted Secure IP (TSIP) | Hardware-accelerated AES256/SHA256 and true random number generation - meets IEC62443-3-3 SL2 requirements. |
| IEC60730 safety functions | Oscillation-stop detection, CRC-A, IWDTa, A/D self-diagnostic - certified for Class B compliance in appliance control. |
| Event Link Controller (ELC) | 99 internal event signals routed without CPU intervention - reduces latency for time-critical sensor-to-PWM response. |
| Capacitive Touch Sensing Unit (CTSU) | Self- and mutual-capacitance modes; 17-pin self-capacitance or 64-key matrix - eliminates need for external touch controller IC. |
Applications
| Industrial HMI Panels | Smart Energy Meters |
|---|---|
Use Scenario: Touch-enabled operator interface with real-time data visualization and local configuration. IC Role / Device Role / Timing Role: Main application processor executing GUI framework, managing CTSU touch inputs, and driving SPI-connected display. Use Value: Integrated CTSU and 120-MHz RXv3 core eliminate external touch controller and enable <10-ms touch response latency. | Use Scenario: Revenue-grade electricity meter with tamper detection, secure firmware updates, and PLC/RF communication. IC Role / Device Role / Timing Role: System-on-chip controller handling metrology calculations (via FPU), secure bootloader, and CAN/RS-485 communications. Use Value: TSIP-based AES256 and dual-bank flash ensure cryptographic integrity and fail-safe field upgrades per DLMS/COSEM standards. |
| Building Automation Controllers | Medical Diagnostic Devices |
Use Scenario: HVAC zone controller with temperature sensing, relay actuation, and BACnet/IP over Ethernet (via external PHY). IC Role / Device Role / Timing Role: Real-time scheduler managing 12-bit ADC sampling, PWM fan control, and CAN bus coordination with field devices. Use Value: MPU-enforced memory isolation prevents firmware corruption during concurrent CAN messaging and UI rendering. | Use Scenario: Portable ultrasound or patient monitor requiring low-power operation, analog signal acquisition, and encrypted data storage. IC Role / Device Role / Timing Role: Central MCU acquiring analog sensor data via S12AD, performing FFT preprocessing using FPU, and storing logs in encrypted data flash. Use Value: On-chip 384 KB SRAM enables real-time waveform buffering; temperature sensor ±1°C accuracy supports thermal drift compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F5670EDGLJ#20 | Same RX671 Group, 512 KB flash (vs. 1 MB), identical peripherals and package - lower memory density. | Suitable for cost-sensitive designs with smaller firmware footprints and no dual-bank requirement. | Select when application code size remains under 400 KB and background flash programming is not needed. |
| R5F566TEADFP#30 | RX66T Group, 160 MHz, 1 MB flash, focused on motor control (3× MTU3, 3-phase PWM), no SDHI or QSPIX. | Optimized for inverters and servo drives; lacks SD/USB/CTSU - unsuitable for HMI or metering. | Choose only for high-performance motor control where R5F5671EDGLJ#20's connectivity and security features are unnecessary. |
Compared with R5F5671EDGLJ#20, R5F5670EDGLJ#20 offers identical peripheral set and pinout but reduced flash capacity, while R5F566TEADFP#30 trades connectivity (no USB/SD/QSPIX) for enhanced motor control timing precision - making R5F5671EDGLJ#20 the sole choice for secure, connected industrial edge nodes requiring both rich I/O and cryptographic acceleration.
Availability
R5F5671EDGLJ#20 is available at Aetrix Electronics and suitable for industrial HMI panels, smart energy meters, building automation controllers, and medical diagnostic devices requiring stable component supply across multi-year production cycles.
Supply support for R5F5671EDGLJ#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX671 Group - including R5F5671EDGLJ#20 - was designed for secure, real-time industrial edge applications demanding high computational throughput, functional safety certification, and integrated connectivity without external co-processors.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F5671EDGLJ#20?
The R5F5671EDGLJ#20 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark. This performance stems from its RXv3 CPU core with optimized pipeline, double-precision FPU, and zero-wait-state access to 384 KB SRAM. The CoreMark benchmark reflects deterministic real-time execution capability - critical for industrial control loops and HMI responsiveness in deployed R5F5671EDGLJ#20 systems.
Does the R5F5671EDGLJ#20 support secure firmware updates, and how is this implemented?
Yes, the R5F5671EDGLJ#20 supports secure firmware updates via its Trusted Secure IP (TSIP) module and dual-bank flash architecture. TSIP provides hardware-accelerated AES256 decryption and SHA256 signature verification, while dual-bank flash allows one bank to execute while the other is programmed - ensuring zero-downtime updates. This combination meets IEC62443-3-3 SL2 requirements and is validated in R5F5671EDGLJ#20 reference designs for smart metering and industrial gateways.
What package type and pin count does the R5F5671EDGLJ#20 use, and is it RoHS compliant?
The R5F5671EDGLJ#20 uses the PLQP0144KA-B package: a 144-pin LFQFP with 20 × 20 mm body and 0.50-mm pitch. It is lead-free and RoHS compliant per Renesas' official product change notice PCN-220001. The package includes an exposed thermal pad for enhanced heat dissipation in industrial enclosures - a key mechanical specification confirmed in the R5F5671EDGLJ#20 datasheet Rev.1.20.
Can the R5F5671EDGLJ#20 directly interface with SD cards, and what speed modes are supported?
Yes, the R5F5671EDGLJ#20 integrates a full SD host interface (SDHI) supporting both 1-bit and 4-bit SD/SDIO buses. It complies with SD Physical Layer Spec v3.01 and supports default speed (12.5 MB/s) and high-speed mode (25 MB/s). No external level shifters or PHYs are required - the SDHI block handles command/data CRC, card detection, and DMA-coordinated transfers, as documented for R5F5671EDGLJ#20 in Section 1.1 of the datasheet.
What is the role of the CTSU in the R5F5671EDGLJ#20, and how many touch keys does it support?
The Capacitive Touch Sensing Unit (CTSU) in the R5F5671EDGLJ#20 enables self- and mutual-capacitance touch detection without external components. In self-capacitance mode, it supports up to 17 independent keys using dedicated CTSU_SOU pins; in mutual-capacitance matrix mode, it supports up to 64 keys using 17 pins. This capability is confirmed in the R5F5671EDGLJ#20 datasheet Section 1.1 and eliminates the need for discrete touch controller ICs in HMI designs.
R5F5671EDGLJ#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-TFLGA
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 80
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EDGLJ#20 FAQ
1.How can I place an order for R5F5671EDGLJ#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EDGLJ#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EDGLJ#20 reliable?
The price and inventory of R5F5671EDGLJ#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EDGLJ#20 is usually 5 days.
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Once your R5F5671EDGLJ#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EDGLJ#20?
For technical support, including R5F5671EDGLJ#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EDGLJ#20 requirements.
6.How does Aetrix verify that R5F5671EDGLJ#20 is sourced from the original manufacturer or authorized distributors?
All R5F5671EDGLJ#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EDGLJ#20 meets industry standards.
7.What is the process for return or replacement of R5F5671EDGLJ#20?
All R5F5671EDGLJ#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EDGLJ#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EDGLJ#20 part is unused and in its original packaging.
Return procedure for R5F5671EDGLJ#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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