My Inquiry
My Account
Renesas R5F5671EHGFB#10
- Part No.:
- R5F5671EHGFB#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R5F5671EHGFB#10.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 144LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,751
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F5671EHGFB#10 from Renesas is a 32-bit RXv3 microcontroller operating at up to 120 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash with dual-bank support, 384 KB SRAM, and integrated CAN, USB 2.0 FS, SD host interface, QSPIX, and capacitive touch sensing - deployed in industrial HMI, smart metering, and connected appliance control systems.
For engineers reviewing the R5F5671EHGFB#10 datasheet, R5F5671EHGFB#10 pinout, R5F5671EHGFB#10 application, or R5F5671EHGFB#10 equivalent, key selection criteria include its 145-pin TFLGA (0.65 mm pitch) package, -40°C to +105°C G-grade temperature rating, IEC60730-compliant safety features (TSIP, MPU, self-diagnostic A/D), and real-time clock with battery-backed operation.
Technical Context
The R5F5671EHGFB#10 implements the RXv3 CPU core with 113 instructions, including 21 double-precision floating-point operations and collective register bank save for fast context switching. Its clock system integrates PLL, sub-clock oscillator (32.768 kHz), and dedicated 120-kHz IWDT oscillator - enabling independent timing domains for ICLK (120 MHz), PCLKA (120 MHz), and PCLKB (60 MHz).
Peripheral architecture includes three DMA controllers (DMACAb: 8 channels, EXDMACa: 2 channels, DTCb: 1 channel), event-link controller (ELC) supporting 99 internal signals, and segmented external bus with 8 CS areas (up to 128 MB SDRAM). The CTSUa supports mutual-capacitance matrix up to 17×, while S12ADFa provides two 12-bit A/D units with self-diagnostic and disconnection detection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 120 MHz max, 707 CoreMark, double-precision FPU, 16 register banks |
| Memory | 2 MB code flash (dual-bank, BGO programming), 8 KB data flash (100k cycles), 384 KB SRAM (no wait states) |
| Package & Temp | PTLG0145JC-A (145-pin TFLGA, 9 × 9 mm, 0.65 mm pitch), G-grade: –40°C to +105°C |
| Peripherals | 2× CAN (32 mailboxes/channel), 1× USB 2.0 FS host/function/OTG, 1× SDHI (25 MB/s), 1× QSPIX, 13× SCI, 3× RSPId, 1× RIICHS (3.4 Mbps) |
| Security & Safety | Trusted Secure IP (TSIP) with AES128/192/256, RSA, ECC, TRNG, SHA256; MPU (8 regions); IEC60730 compliance support |
| Analog & Timing | Two 12-bit S12AD units (8+12 ch), CTSUa (17-key self-cap or 64-key mutual-cap), RTC with battery backup, 25+ timers including MTU3a and TPUa |
Pinout & Package
PTLG0145JC-A is a 145-pin thin fine-pitch land grid array (TFLGA) package measuring 9 × 9 mm with 0.65 mm pitch, designed for high-density PCB layouts and thermal efficiency in industrial control modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog domain supplies (2.7–3.6 V); AVCC0/AVCC1 power analog peripherals including A/D and RTC |
| VBATT | Backup power input | Enables RTC, backup registers, and sub-clock oscillator during main power loss |
| RES# | Active-low reset input | Hardware reset assertion; internal POR/LVD also generate reset independently |
| CLKIN, CLKOUT | External crystal interface | Supports 8–24 MHz crystal for main clock oscillator; CLKOUT provides buffered system clock output |
| USB_DP, USB_DM | USB 2.0 full-speed differential pair | Integrated transceiver eliminates need for external pull-ups; supports host/function/OTG modes |
| SD0_CMD, SD0_CLK, SD0_DAT0–3 | SD host interface signals | 1- or 4-bit SD bus interface compliant with SD Physical Layer Spec v3.01 (no DDR) |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates via bank swap without halting execution - critical for OTA-capable industrial gateways |
| Trusted Secure IP (TSIP) | Hardware-accelerated crypto engine with key protection prevents firmware cloning and enables secure boot verification |
| Capacitive touch sensing unit (CTSUa) | Supports mutual-capacitance matrix up to 17× (64 keys) with built-in noise rejection - eliminates external touch controller in HMI designs |
| IEC60730-compliant safety functions | Includes oscillation-stop detection, CRC-accelerated memory checking, A/D self-diagnostic, and register write protection for Class B certification |
| Event Link Controller (ELC) | 99 internal event signals routed without CPU intervention - reduces latency for time-critical sensor-to-PWM response (e.g., motor control) |
Applications
| Industrial HMI Panels | Smart Energy Meters |
|---|---|
|
Use Scenario: Touch-enabled front-panel interface with real-time energy display, tariff switching, and tamper detection. IC Role / Device Role / Timing Role: Main application MCU handling GUI rendering, capacitive touch decoding, RTC-based billing cycles, and secure firmware updates. Use Value: Integrated CTSUa and TSIP eliminate external touch controller and crypto IC; dual-bank flash enables field-upgradable meter firmware without service interruption. |
Use Scenario: DIN-rail mounted electricity meter with pulse counting, communication via CAN/RS485, and secure data logging. IC Role / Device Role / Timing Role: System controller managing metrology interface (via SPI), CAN bus for utility network, and encrypted storage of consumption history. Use Value: 2 MB flash stores full firmware + encrypted logs; TSIP ensures data integrity per IEC62056; 12-bit A/D supports auxiliary sensor monitoring. |
| Connected Home Appliances | Building Automation Controllers |
|
Use Scenario: Wi-Fi/BLE gateway appliance (e.g., HVAC controller) requiring local decision logic, USB diagnostics, and SD card logging. IC Role / Device Role / Timing Role: Local intelligence hub interfacing with sensors, executing control algorithms, and buffering logs to SD card via SDHI. Use Value: SDHI (25 MB/s) enables rapid firmware recovery from SD; USB 2.0 FS simplifies field service; 384 KB SRAM accommodates RTOS + protocol stacks. |
Use Scenario: BACnet/IP or KNX gateway aggregating Modbus RTU devices, performing schedule-based HVAC control, and reporting to cloud. IC Role / Device Role / Timing Role: Protocol translation engine with CAN, RS485 (SCI), and Ethernet MAC interface (external PHY), plus RTC-synchronized scheduling. Use Value: 13-channel SCI supports multiple legacy field buses; RTC with battery backup maintains schedules during power loss; MPU isolates protocol stacks for reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F566TEHGFB#10 | Same RX66T core family but lower max frequency (160 MHz vs 120 MHz), no TSIP, 1 MB flash, no SDHI or QSPIX | Targeted at motor control only; lacks security, storage, and HMI peripherals needed for R5F5671EHGFB#10's use cases | Select only when cost-sensitive motor drive is sole requirement and security/storage not needed |
| R7FA6M2AF3CFB#AA0 | RXv3-based RA6M2 (Arm Cortex-M4F), 100 MHz, 1 MB flash, 256 KB SRAM, no CTSU or TSIP, supports TrustZone | Arm ecosystem alignment preferred; lacks integrated touch and hardware crypto acceleration of TSIP | Choose for Arm toolchain continuity or where TrustZone suffices instead of TSIP-level key protection |
Compared with R5F5671EHGFB#10, the R5F566TEHGFB#10 omits security and storage interfaces essential for certified metering, while the R7FA6M2AF3CFB#AA0 trades TSIP and CTSU for Arm compatibility and TrustZone - making R5F5671EHGFB#10 uniquely suited for secure, touch-enabled, SD/QSPIX-equipped industrial edge nodes.
Availability
R5F5671EHGFB#10 is available at Aetrix Electronics and suitable for industrial HMI, smart metering, and building automation applications requiring stable component supply, long lifecycle assurance, and automotive-grade temperature resilience.
Supply support for R5F5671EHGFB#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX671 Group - including R5F5671EHGFB#10 - is engineered for high-integrity industrial edge applications demanding real-time performance, functional safety, cryptographic security, and rich human-machine interface capabilities.
FAQ
What is the maximum operating frequency and core architecture of the R5F5671EHGFB#10?
The R5F5671EHGFB#10 operates at a maximum frequency of 120 MHz using the 32-bit RXv3 CPU core, delivering 707 CoreMark performance. It includes double-precision IEEE-754 floating-point support, 113 instructions (including DSP and FPU extensions), and a collective register bank save function enabling fast interrupt response. This architecture is optimized for deterministic real-time control in industrial applications.
Which package and temperature grade does the R5F5671EHGFB#10 use?
R5F5671EHGFB#10 uses the PTLG0145JC-A package: a 145-pin thin fine-pitch land grid array (TFLGA) measuring 9 × 9 mm with 0.65 mm pitch. It is rated for the G-grade industrial temperature range of –40°C to +105°C, making it suitable for deployment in harsh environments such as factory floors and outdoor metering enclosures.
Does the R5F5671EHGFB#10 support secure firmware updates and cryptographic operations?
Yes, the R5F5671EHGFB#10 integrates Trusted Secure IP (TSIP) supporting AES128/192/256, RSA, ECC, SHA256, and a true random number generator (TRNG). Its dual-bank flash enables background firmware updates with bank swapping, while TSIP protects keys from illicit copying and accelerates secure boot verification - fulfilling IEC60730 Class B requirements.
What communication interfaces are available on the R5F5671EHGFB#10 for industrial connectivity?
The R5F5671EHGFB#10 provides extensive industrial connectivity: 2× CAN (ISO11898-1, 32 mailboxes/channel), 1× USB 2.0 FS host/function/OTG, 1× SD host interface (25 MB/s), 1× QSPIX for serial flash, 13× SCI (including LIN/Manchester), 3× RSPId, 1× RIICHS (3.4 Mbps), and 2× RSCI with HBS support - enabling robust multi-protocol fieldbus integration.
How does the R5F5671EHGFB#10 support capacitive touch and analog sensing in HMI applications?
R5F5671EHGFB#10 integrates a dedicated Capacitive Touch Sensing Unit (CTSUa) supporting up to 64 keys via mutual-capacitance matrix (17 pins), with built-in noise cancellation. It also includes two 12-bit A/D converters (S12ADFa) with self-diagnostic, disconnection detection, and programmable sampling - enabling reliable touch panels and auxiliary sensor monitoring without external components.
R5F5671EHGFB#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RX671
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, I2C, LINbus, QSPI, SCI, SPI, USB
- Peripherals:
- Capacitive Touch, DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 113
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F5671EHGFB#10 FAQ
1.How can I place an order for R5F5671EHGFB#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F5671EHGFB#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F5671EHGFB#10 reliable?
The price and inventory of R5F5671EHGFB#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F5671EHGFB#10 is usually 5 days.
3.What payment methods are accepted for R5F5671EHGFB#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F5671EHGFB#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F5671EHGFB#10?
R5F5671EHGFB#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F5671EHGFB#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F5671EHGFB#10?
For technical support, including R5F5671EHGFB#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F5671EHGFB#10 requirements.
6.How does Aetrix verify that R5F5671EHGFB#10 is sourced from the original manufacturer or authorized distributors?
All R5F5671EHGFB#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F5671EHGFB#10 meets industry standards.
7.What is the process for return or replacement of R5F5671EHGFB#10?
All R5F5671EHGFB#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F5671EHGFB#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F5671EHGFB#10 part is unused and in its original packaging.
Return procedure for R5F5671EHGFB#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F5671EHGFB#10 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
