Renesas R5F5671EHGFM#10

Overview

R5F5671EHGFM#10 from Renesas is a 120-MHz 32-bit RXv3 microcontroller with double-precision IEEE-754 FPU, 2 Mbytes of dual-bank code flash, 384 Kbytes of zero-wait-state SRAM, and integrated capacitive touch sensing unit (CTSU) supporting up to 64 keys via mutual capacitance. It targets industrial HMI, secure IoT edge nodes, and automotive body control modules requiring IEC60730 compliance, USB 2.0 FS host/function, CAN 2.0B, and SD host interface.

For engineers reviewing the R5F5671EHGFM#10 datasheet, R5F5671EHGFM#10 pinout, R5F5671EHGFM#10 application, or R5F5671EHGFM#10 equivalent, key selection considerations include its 145-pin TFLGA package (7 × 7 mm, 0.50-mm pitch), -40°C to +105°C operating range (G-version), TSIP-based AES256/SHA256/RSA encryption, and real-time clock with battery-backed operation - all validated in Renesas R01DS0373EJ0120 Rev.1.20.

Technical Context

The R5F5671EHGFM#10 implements the RXv3 CPU core with 113 instructions, 16 general-purpose 32-bit registers, and dual-precision FPU supporting 21 double-precision floating-point instructions. Its memory subsystem includes 2 Mbytes of code flash with ROM cache (8 Kbytes), 8 Kbytes of data flash rated for 100,000 erase/write cycles, and 384 Kbytes of SRAM accessible at full 120 MHz without wait states.

Peripherals are clocked across four domains: ICLK (up to 120 MHz for CPU/QSPIX), PCLKA (up to 120 MHz for MTU/RSPI/RIICHS), PCLKB (up to 60 MHz for most timers and interfaces), and PCLKC/PCLKD (up to 60 MHz for S12AD units). The device integrates TSIP for hardware-accelerated cryptographic operations and supports IEC60730 Class B self-test via CRC, IWDTa, and A/D converter diagnostics.

Key Specifications

Pinout & Package

Package: TFLGA-145 (PTLG0145KB-A), 7 × 7 mm, 0.50-mm pitch, 0.75-mm height, lead-free, RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit MCU applications.

Compared with R5F5671EHGFM#10, the R5F5670EHGFM#10 offers reduced memory at lower cost without sacrificing security or peripherals, while the R5F566TEHGFM#10 trades TSIP and CTSU for higher clock speed and motor-specific timers - making it incompatible for touch/crypto applications despite shared packaging.

Availability

R5F5671EHGFM#10 is available at Aetrix Electronics and suitable for industrial HMI, secure IoT gateways, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for R5F5671EHGFM#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.

The RX671 Group, including R5F5671EHGFM#10, was designed for secure, real-time embedded applications demanding high computational throughput, robust functional safety, and rich human-machine interface capabilities - especially where touch, cryptography, and mixed-signal integration are critical.

FAQ

What is the maximum operating frequency and CoreMark score of the R5F5671EHGFM#10?

The R5F5671EHGFM#10 operates at a maximum frequency of 120 MHz and achieves 707 CoreMark points under benchmark conditions. This performance stems from the RXv3 CPU core's optimized instruction pipeline, dual-precision FPU, and zero-wait-state access to 384 Kbytes of SRAM - all confirmed in Renesas R01DS0373EJ0120 Rev.1.20. The R5F5671EHGFM#10 delivers deterministic real-time response for time-critical control loops.

Does the R5F5671EHGFM#10 support hardware-based cryptographic acceleration?

Yes, the R5F5671EHGFM#10 integrates Trusted Secure IP (TSIP) that provides hardware-accelerated AES128/192/256, RSA, ECC, SHA1/224/256, MD5, and TRNG functions. TSIP protects keys from extraction and enables secure boot, encrypted firmware updates, and authenticated communication - all without consuming CPU cycles. This capability is documented in Section 1.1 and Chapter 37 of the R5F5671EHGFM#10 datasheet.

What package type and pin count does the R5F5671EHGFM#10 use?

The R5F5671EHGFM#10 uses a 145-pin TFLGA package (PTLG0145KB-A), measuring 7 × 7 mm with 0.50-mm pitch and 0.75-mm height. It provides 113 general-purpose I/O pins, including 20 with 5-V tolerance, and supports -40°C to +105°C operation. This package is explicitly listed in Table 1.2 of the R5F5671EHGFM#10 datasheet and matches the "G-version" temperature grade.

Can the R5F5671EHGFM#10 execute code directly from external quad-SPI flash?

Yes, the R5F5671EHGFM#10 includes a QSPIX interface that supports direct code execution (XIP) from external quad-SPI flash memory. It implements extended SPI, dual-SPI, and quad-SPI protocols with selectable address widths (8–32 bits), enabling fast, low-pin-count expansion of program memory. This feature is detailed in Section 1.1 and Chapter 33 of the R5F5671EHGFM#10 datasheet.

How many channels does the capacitive touch sensing unit (CTSU) support on the R5F5671EHGFM#10?

The R5F5671EHGFM#10's CTSU supports up to 64 keys using mutual capacitance mode with a 17-pin matrix configuration, or up to 17 keys in self-capacitance mode. This is enabled by dedicated CTSU hardware with built-in noise cancellation and automatic calibration - eliminating need for external touch controllers. The specification is confirmed in Section 1.1 and Chapter 35 of the R5F5671EHGFM#10 datasheet.