Renesas R5F571MJGDLK#20
- Part No.:
- R5F571MJGDLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F571MJGDLK#20.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
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Product details
Overview
R5F571MJGDLK#20 from Renesas is a 32-bit RXv2 microcontroller operating at up to 240 MHz, delivering 480 DMIPS with integrated single-precision IEEE-754 FPU, 4 MB on-chip code flash, 512 KB SRAM (including 32 KB ECC RAM), and dual 12-bit A/D converters (8 + 21 channels). It serves as a high-integration control and connectivity hub in industrial gateways requiring real-time Ethernet, CAN, USB HS, and secure firmware execution.
For engineers reviewing the R5F571MJGDLK#20 datasheet, R5F571MJGDLK#20 pinout, R5F571MJGDLK#20 application, or R5F571MJGDLK#20 equivalent, this MCU supports IEEE 1588-compliant Ethernet MAC (dual-channel), ISO 11898-1 CAN (3 modules), high-speed USB 2.0 with battery charging, SD host interface, quad SPI, hardware AES/SHA encryption, and IEC 60730 safety features - all within a 176-pin LFBGA package rated for –40°C to +105°C operation.
Technical Context
The R5F571MJGDLK#20 implements the RXv2 CPU core with CISC Harvard architecture, 5-stage pipeline, and variable-length instructions enabling ultra-compact code density. It integrates dual clock domains: ICLK up to 240 MHz for CPU execution and PCLKA up to 120 MHz for Ethernet, USB, CAN, and AES peripherals - enabling deterministic real-time processing while maintaining peripheral bandwidth.
Its memory subsystem includes 4 MB code flash with zero-wait access ≤120 MHz (AFU-hit), 64 KB data flash (100,000 write cycles), 512 KB SRAM (with 256 KB no-wait at 240 MHz), and 32 KB ECCRAM supporting SEC-DED error correction. The device supports four low-power modes, RTC with battery backup, and independent watchdog timer (IWDTa) with windowed refresh for functional safety compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv2 32-bit CISC Harvard core with 5-stage pipeline, 480 DMIPS @ 240 MHz |
| Max Clock Frequency | 240 MHz system clock (ICLK); PCLKA up to 120 MHz for Ethernet/USB/CAN |
| Memory | 4 MB code flash (no-wait ≤120 MHz), 64 KB data flash, 512 KB SRAM, 32 KB ECCRAM |
| Analog Peripherals | Dual 12-bit S12ADC (8 + 21 channels), 2×12-bit D/A, on-chip temperature sensor |
| Connectivity | Dual IEEE 1588 Ethernet MAC, 3×CAN (ISO 11898-1), USB 2.0 HS + FS (OTG), SDHI, QSPI, 2×RIIC, 9×SCIg/h, 4×SCIFA |
| Security & Safety | Hardware AES-128/192/256, DES/TDES, SHA-1/224/256, CRC, IWDTa with windowing, MPU, self-diagnostic A/D |
| Package & Temp | LFBGA-176 (PLQP0176KB-A, 24 × 24 mm, 0.5-mm pitch), G-version: –40°C to +105°C |
Pinout & Package
Package: PLQP0176KB-A, 176-pin LFBGA, 24 × 24 mm, 0.5-mm pitch, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, AVCC0, AVCC1 | Power supply inputs | Core/analog supply (2.7–3.6 V); separate analog domains enable noise isolation for ADC/DAC |
| VBATT | Battery backup input | Supplies RTC during main power loss; enables calendar/timekeeping in deep software standby |
| XTAL/EXTAL | Main crystal oscillator terminals | Supports 8–24 MHz external crystal for precise system timing and Ethernet PTP synchronization |
| MD0–MD2 | Mode setting pins | Determine boot mode (single-chip, SCI/USB boot, user boot) at reset release |
| ETH_MDC/MDIO | Ethernet management interface | IEEE 802.3 MII/RMII management interface for PHY configuration and status monitoring |
| USBA_VBUS, USBA_DP/DN | USB 2.0 HS transceiver interface | Dedicated high-speed USB physical layer (480 Mbps) with integrated transceiver and 8.5 KB buffer |
| SD0_CLK/SD0_CMD/SD0_DAT[0:3] | SD host interface signals | 1–4-bit SD bus interface compliant with SD Physical Layer Spec v3.01 (high-speed mode: 15 MB/s) |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 PTP Hardware Acceleration | EPTPCa block provides timestamping with sub-microsecond accuracy for time-critical industrial networking |
| Functional Safety Support | IEC 60730-compliant features: oscillation-stop detection, CRC engine, IWDTa with windowing, A/D self-diagnostic |
| Secure Firmware Execution | Trusted Memory (TM) blocks 8–9 protect against unauthorized read-out; hardware crypto accelerates AES/SHA |
| Real-Time Determinism | ELC (Event Link Controller) enables direct peripheral-to-peripheral triggering without CPU intervention |
| Flexible Power Management | Four low-power modes including deep software standby with 8 KB retained RAM and RTC battery backup |
Applications
| Industrial Ethernet Gateway | Smart Energy Metering Hub |
|---|---|
|
Use Scenario: Aggregating Modbus TCP, CANopen, and BACnet MS/TP traffic across fieldbus networks into a unified IEEE 1588-synchronized Ethernet backbone. IC Role / Device Role / Timing Role: Primary protocol translation and time-aware packet forwarding engine with hardware-accelerated PTP timestamping and dual Ethernet MACs. Use Value: Enables sub-1 µs time synchronization across distributed sensors/actuators without external timing hardware or CPU overhead. |
Use Scenario: Multi-tariff electricity meter with tamper detection, waveform analysis, and remote firmware updates via cellular backhaul. IC Role / Device Role / Timing Role: Secure metering controller handling real-time sampling (dual 12-bit ADC), cryptographic signing of consumption logs, and OTA update validation. Use Value: Hardware AES/SHA and trusted memory prevent firmware rollback or unauthorized parameter modification per IEC 62056-53. |
| Programmable Logic Controller (PLC) CPU Module | Automated Test Equipment (ATE) Sequencer |
|
Use Scenario: Compact PLC base unit executing ladder logic, motion control, and HMI communication over EtherCAT or PROFINET. IC Role / Device Role / Timing Role: Real-time deterministic controller with MTU3/GPT PWM generation, CAN for fieldbus I/O, and USB HS for configuration download. Use Value: 240 MHz RXv2 core + ELC eliminates jitter in servo loop timing; 32 KB ECCRAM ensures reliable runtime data integrity. |
Use Scenario: High-precision signal stimulus and measurement platform validating mixed-signal ICs using programmable waveforms and FFT analysis. IC Role / Device Role / Timing Role: Precision timing sequencer generating synchronized trigger events for DAC output, ADC capture, and digital pattern generation. Use Value: TPUa/MTU3 event linking and PDC interface enable <100 ns inter-peripheral timing alignment without CPU polling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F571MLGDLK#20 | Same RX71M family, identical pinout and peripherals, but with 2.5 MB code flash instead of 4 MB | Suitable where firmware footprint is <2.5 MB and cost optimization is prioritized over future scalability | Select when flash headroom is not required and BOM cost reduction is critical |
| R5F572MHGDLK#20 | RX72M family successor: higher 400 MHz CPU, enhanced security (TRNG, secure boot), same 176-pin LFBGA | Targets next-gen designs needing higher compute throughput, advanced security certification, or longer product lifecycle | Choose for new designs requiring >480 DMIPS, PSA Level 2 certification, or extended roadmap support |
Compared with R5F571MJGDLK#20, R5F571MLGDLK#20 reduces flash capacity without altering timing or peripheral behavior, while R5F572MHGDLK#20 upgrades CPU performance and security architecture - both retain identical pinout and thermal profile for drop-in evaluation, though only the latter supports PSA-certified secure boot.
Availability
R5F571MJGDLK#20 is available at Aetrix Electronics and suitable for industrial gateways, smart energy meters, PLC CPU modules, and automated test equipment requiring stable component supply across extended product lifecycles.
Supply support for R5F571MJGDLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX71M Group targets high-reliability industrial automation applications demanding real-time determinism, functional safety compliance (IEC 60730), and rich connectivity - combining high-speed CPU performance with hardware-accelerated Ethernet, CAN, and security engines.
FAQ
What is the maximum operating frequency and DMIPS rating of the R5F571MJGDLK#20?
The R5F571MJGDLK#20 operates at a maximum system clock frequency of 240 MHz and delivers 480 DMIPS (Dhrystone MIPS) under benchmark conditions. This performance stems from its RXv2 CPU core with 5-stage pipeline, single-cycle 32-bit multiply, and optimized instruction set - enabling real-time control loops and protocol stack processing without external co-processors. The R5F571MJGDLK#20 maintains this rating across its full industrial temperature range (–40°C to +105°C).
Does the R5F571MJGDLK#20 support IEEE 1588 Precision Time Protocol hardware acceleration?
Yes, the R5F571MJGDLK#20 integrates a dedicated EPTPCa (Ethernet PTP Controller) block compliant with IEEE 1588-2008, providing hardware timestamping for transmit and receive Ethernet frames with sub-microsecond accuracy. This capability is tightly coupled with the dual ETHERC modules and enables deterministic time synchronization in industrial Ethernet applications such as motion control and distributed I/O - without consuming CPU cycles for timestamp insertion or correction.
What are the flash and RAM configurations of the R5F571MJGDLK#20?
The R5F571MJGDLK#20 includes 4 MB of on-chip code flash memory (zero-wait access up to 120 MHz), 64 KB of reprogrammable data flash (rated for 100,000 erase/write cycles), 512 KB of general-purpose SRAM (with 256 KB accessible at full 240 MHz speed), and 32 KB of ECC-protected RAM supporting single-error correction and double-error detection. These memory resources are mapped to linear 4 GB address space and managed by an integrated memory protection unit (MPU) for robust multitasking.
Which communication interfaces does the R5F571MJGDLK#20 support for industrial connectivity?
The R5F571MJGDLK#20 supports dual IEEE 1588-compliant Ethernet MACs, three ISO 11898-1 CAN controllers (32 mailboxes each), high-speed USB 2.0 (480 Mbps) with battery charging and OTG, SD host interface (15 MB/s), quad SPI, two I²C buses (up to 1 Mbps), nine SCI channels (with smart-card and simplified SPI/I²C modes), and four SCIFA interfaces with 16-byte FIFOs. This combination enables seamless integration into heterogeneous industrial networks without external bridge ICs.
Is the R5F571MJGDLK#20 qualified for functional safety standards like IEC 60730?
Yes, the R5F571MJGDLK#20 includes multiple hardware features certified for Class B compliance with IEC 60730-1, including oscillation-stop detection, hardware CRC calculation unit, independent watchdog timer (IWDTa) with configurable windowing, self-diagnostic A/D converter, register write protection, and memory protection unit (MPU). These capabilities are documented in Renesas' Functional Safety Manual (R01UM0124EJ0200) and enable safe monitoring of critical control functions in household and industrial appliances.
R5F571MJGDLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX71M
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv2
- Core Size:
- 32-Bit Single-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 8x12b, 21x12b; D/A 2x12
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F571MJGDLK#20 FAQ
1.How can I place an order for R5F571MJGDLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F571MJGDLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F571MJGDLK#20 reliable?
The price and inventory of R5F571MJGDLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F571MJGDLK#20 is usually 5 days.
3.What payment methods are accepted for R5F571MJGDLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F571MJGDLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
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R5F571MJGDLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F571MJGDLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F571MJGDLK#20?
For technical support, including R5F571MJGDLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F571MJGDLK#20 requirements.
6.How does Aetrix verify that R5F571MJGDLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F571MJGDLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F571MJGDLK#20 meets industry standards.
7.What is the process for return or replacement of R5F571MJGDLK#20?
All R5F571MJGDLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F571MJGDLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F571MJGDLK#20 part is unused and in its original packaging.
Return procedure for R5F571MJGDLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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