Renesas R5F572NDDDBG#20
- Part No.:
- R5F572NDDDBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F572NDDDBG#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:133
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Product details
Overview
R5F572NDDDBG#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 240 MHz, featuring double-precision IEEE-754 FPU, 2 MB on-chip code flash, 1 MB SRAM (512 KB + 512 KB expansion), and integrated Ethernet MAC compliant with IEEE 1588. It supports CAN (ISO 11898-1), USB 2.0 FS host/function, SDHI, QSPI, and GLCDC - deployed in industrial HMIs, networked PLCs, and real-time motion controllers.
For engineers reviewing the R5F572NDDDBG#20 datasheet, R5F572NDDDBG#20 pinout, R5F572NDDDBG#20 application, or R5F572NDDDBG#20 equivalent, key selection criteria include IEEE 1588 PTP timing accuracy, dual-bank flash for safe firmware updates, 182 GPIO with 5-V tolerance, ECC-protected RAM, and hardware-accelerated trigonometric (TFU) and AES encryption functions.
Technical Context
The R5F572NDDDBG#20 implements the RXv3 CPU core with 16×32-bit general-purpose registers, 2×72-bit accumulators, and 113 instructions including DSP and floating-point extensions. Its memory subsystem integrates 2 MB code flash (dual-bank, BGO-capable), 32 KB data flash (100k write cycles), 512 KB SRAM + 512 KB expansion RAM (both no-wait ≤120 MHz), and 32 KB ECC RAM with SEC-DED.
Peripherals are clocked across four domains: ICLK (up to 240 MHz for CPU), PCLKA (up to 120 MHz for ETHERC/GPTW/GLCDC), PCLKB (up to 60 MHz for TMR/CMT/SCIi), and PCLKC/PCLKD (60 MHz for S12AD units). The ELC enables deterministic event chaining between 135 internal signals without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 240 MHz max, 1396 CoreMark, double-precision FPU, MPU support |
| Memory | 2 MB code flash (dual-bank, BGO), 32 KB data flash (100k cycles), 1 MB SRAM (512 KB + 512 KB), 32 KB ECC RAM |
| Connectivity | Ethernet MAC ×2 (IEEE 1588 PTP), CAN ×3 (32 mailboxes/channel), USB 2.0 FS host/function, SDHI, QSPI, RIIC ×3, SCI ×13 |
| Timers & PWM | GPTW ×4 (32-bit), MTU3a ×9 (16/32-bit), TPUa ×6, CMTW ×2, IWDTa + WDTA, RTC with battery backup |
| Analog | S12AD ×2 (8 + 21 channels, self-diagnostic), D/A ×2 (12-bit), on-die temperature sensor |
| Security & Acceleration | TFU (sine/cosine/arctan), optional TSIP/AES-128/192/256, register write protection, IEC60730 diagnostic features |
| Package & I/O | LFBGA-224 (13 × 13 mm, 0.8-mm pitch), 182 GPIO, 5-V tolerant on 19 pins, open-drain, pull-up configurable |
Pinout & Package
Package: PLBG0224GA-A, 224-pin LFBGA, 13 mm × 13 mm, 0.8-mm pitch, –40°C to +105°C (G-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | 2.7–3.6 V main supply; separate analog rails enable noise-sensitive ADC operation |
| VBATT | Battery backup input | Supplies RTC during main power loss; retains calendar/time and 8 KB standby RAM |
| RES# | Active-low reset input | Hardware reset assertion; internally pulled up; compatible with open-drain reset supervisors |
| CLKIN / CLKOUT | External crystal interface | Supports 8–24 MHz crystal; enables precise clock source for IEEE 1588 timestamping |
| ETXD0–7 / ERXD0–7 | Ethernet PHY data bus | 8-bit parallel MII interface for channel 0; RMII supported via pin multiplexing |
| USB_DP / USB_DM | USB 2.0 differential pair | Full-speed (12 Mbps) transceiver integrated; no external PHY required |
| SD_CLK / SD_CMD / SD_DAT0–3 | SD host interface signals | 4-bit SD bus supporting high-speed mode (25 MB/s); CRC7/CRC16 error detection built-in |
| QSPI_IO0–3 / QSPI_SCK / QSPI_SSL | Quad SPI interface | Direct connection to quad-flash devices; supports single/dual/quad I/O modes with configurable phase/polarity |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash architecture | Enables seamless firmware updates: execute from Bank A while programming Bank B, eliminating system downtime |
| IEEE 1588 Precision Time Protocol (PTP) | Hardware timestamping in ETHERC + EPTPC allows sub-microsecond synchronization across industrial Ethernet networks |
| Event Link Controller (ELC) | Chains 135 internal events (e.g., timer overflow → ADC trigger → DMA transfer) without CPU involvement, reducing latency and ISR load |
| Trigonometric Function Unit (TFU) | Hardware acceleration for sine, cosine, and arctangent - critical for real-time motor control and servo algorithms |
| IEC60730 Class B compliance support | Includes oscillation-stop detection, CRC calculation unit, IWDT windowing, A/D self-test, and register lock bits for safety-critical firmware |
| Graphics LCD controller (GLCDC) | Direct drive of RGB/TFT panels up to WXGA; supports alpha blending, layer composition, and 2D drawing engine (DRW2D) offload |
Applications
| Industrial HMI | Networked PLC Controller |
|---|---|
|
Use Scenario: Touch-enabled operator panel with real-time visualization, local logic execution, and remote diagnostics over Ethernet. IC Role / Device Role / Timing Role: Main application processor managing GLCDC display, touch controller interface, Ethernet stack, and deterministic control loop via GPTW/MTU3a timers. Use Value: Integrated GLCDC + DRW2D eliminates external graphics IC; IEEE 1588 enables synchronized multi-panel time-stamping for audit trails. |
Use Scenario: Compact programmable logic controller with EtherNet/IP or PROFINET connectivity, local I/O expansion, and motion profiling. IC Role / Device Role / Timing Role: Central controller running real-time OS, executing ladder logic, managing CAN-based I/O modules, and synchronizing axis motion via PTP. Use Value: Dual Ethernet MACs allow redundant ring topology; hardware TFU accelerates position interpolation; 182 GPIO support modular digital/analog I/O. |
| Smart Energy Gateway | Embedded Vision Edge Node |
|
Use Scenario: Substation gateway aggregating Modbus RTU/TCP, DLMS/COSEM, and IEC 61850 data for cloud telemetry and local SCADA. IC Role / Device Role / Timing Role: Secure communications hub with TLS offload (AES), multiple serial protocols (SCI/RSPI), SDHI for log storage, and RTC for time-stamped event logging. Use Value: On-chip TSIP provides secure key storage and AES acceleration; dual CAN channels interface legacy metering buses; ECC RAM ensures data integrity. |
Use Scenario: Low-latency camera processing node capturing CMOS sensor data, performing edge analytics, and streaming metadata over Ethernet. IC Role / Device Role / Timing Role: Image acquisition controller using PDC for parallel sensor interface, DRW2D for overlay rendering, and ETHERC for compressed frame transmission. Use Value: PDC supports 8-bit parallel camera input with HSYNC/VSYNC sync; GLCDC overlays UI on video stream; 240 MHz CPU handles lightweight CNN inference. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MNDDBG#20 | Same RX72N Group, identical package and pinout, but with 4 MB code flash and 1 MB SRAM (vs. 2 MB flash / 1 MB SRAM) | Required where larger firmware image size or extended data buffering is needed (e.g., OTA update staging, protocol stack caching) | Select R5F572MNDDBG#20 when >2 MB flash is mandatory; otherwise R5F572NDDDBG#20 offers optimal cost/performance balance for most HMI/PLC designs |
| R5F566TKEDFP#30 | RX66T Group, 160 MHz, 1 MB flash, no Ethernet MAC or GLCDC, includes dedicated motor control timers (MTU3b) and encoder interfaces | Targeted at servo drives and inverters requiring high-resolution PWM and encoder feedback - lacks networking and graphics peripherals | Choose R5F566TKEDFP#30 only for motor-control-dominant applications; R5F572NDDDBG#20 is superior for connected, visualized industrial systems |
Compared with R5F572MNDDBG#20, the R5F572NDDDBG#20 reduces flash capacity by 2 MB but maintains identical peripheral set, timing performance, and package - making it ideal for cost-sensitive deployments where firmware fits in 2 MB. Against R5F566TKEDFP#30, it trades motor-specific timers for full Ethernet, graphics, and security IP - prioritizing connectivity and UI over raw PWM precision.
Availability
R5F572NDDDBG#20 is available at Aetrix Electronics and suitable for industrial HMIs, networked PLCs, and smart energy gateways requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability under extended temperature conditions.
Supply support for R5F572NDDDBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and infrastructure markets.
The RX72N Group - including the R5F572NDDDBG#20 - was designed for high-performance, connected industrial equipment demanding real-time control, rich human-machine interaction, and deterministic networking with IEEE 1588 support.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F572NDDDBG#20?
The R5F572NDDDBG#20 operates at a maximum frequency of 240 MHz and achieves 1396 CoreMark points under benchmark conditions. This performance stems from the RXv3 CPU core's 113-instruction set, dual-issue capability for certain operations, and zero-wait-state access to on-chip SRAM and flash cache at ≤120 MHz - enabling deterministic real-time response in industrial control loops.
Does the R5F572NDDDBG#20 support IEEE 1588 Precision Time Protocol?
Yes, the R5F572NDDDBG#20 supports IEEE 1588 PTP through its integrated Ethernet MAC (ETHERC) and dedicated PTP module (EPTPCb). Hardware timestamping is applied to ingress/egress frames with sub-microsecond resolution, and PTP event matching can trigger MTU or GPTW counters - essential for time-synchronized automation across distributed I/O and motion axes.
What type of memory configuration does the R5F572NDDDBG#20 include?
The R5F572NDDDBG#20 integrates 2 MB of code flash memory with dual-bank structure and background operation (BGO), 32 KB of reprogrammable data flash (100,000 cycles), 1 MB of SRAM (split as 512 KB + 512 KB expansion), 32 KB of ECC-protected RAM, and 8 KB of battery-backed standby RAM. This hierarchy balances speed, endurance, and safety-critical data retention.
Which communication interfaces are available on the R5F572NDDDBG#20?
The R5F572NDDDBG#20 provides two IEEE 1588-compliant Ethernet MACs, three CAN 2.0B channels (32 mailboxes each), one USB 2.0 FS host/function controller, SD host interface (SDHI), quad SPI (QSPI), three I²C channels (RIIC), 13 serial channels (SCIj/i/h), three RSPI, and two SSIE audio interfaces - enabling comprehensive connectivity for industrial gateways and multi-protocol edge devices.
Is the R5F572NDDDBG#20 suitable for IEC 60730 Class B safety certification?
Yes, the R5F572NDDDBG#20 includes multiple hardware features required for IEC 60730 Class B compliance: oscillation-stop detection, independent watchdog timer (IWDTa) with windowing, CRC calculation unit (CRCA), self-diagnostic A/D test mode, register write protection, and memory ECC - all documented in Renesas' functional safety manual R01US0424EJ0100.
R5F572NDDDBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX72N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NDDDBG#20 FAQ
1.How can I place an order for R5F572NDDDBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NDDDBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NDDDBG#20 reliable?
The price and inventory of R5F572NDDDBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NDDDBG#20 is usually 5 days.
3.What payment methods are accepted for R5F572NDDDBG#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NDDDBG#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F572NDDDBG#20?
R5F572NDDDBG#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NDDDBG#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NDDDBG#20?
For technical support, including R5F572NDDDBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NDDDBG#20 requirements.
6.How does Aetrix verify that R5F572NDDDBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NDDDBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NDDDBG#20 meets industry standards.
7.What is the process for return or replacement of R5F572NDDDBG#20?
All R5F572NDDDBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NDDDBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NDDDBG#20 part is unused and in its original packaging.
Return procedure for R5F572NDDDBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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