Renesas R5F572NDDGFC#V0
- Part No.:
- R5F572NDDGFC#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LQFP
- Datasheet:
-
R5F572NDDGFC#V0.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:120
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Product details
Overview
R5F572NDDGFC#V0 from Renesas Electronics is a 32-bit RXv3 core microcontroller in the RX72N Group, featuring 4 MB flash memory, 1 MB SRAM, dual-bank operation for safe firmware updates, and integrated Ethernet MAC with IEEE 1588 timestamping. It operates at up to 240 MHz, supports USB 2.0 FS/HS, CAN FD, and includes hardware encryption (AES-128/256, SHA, RSA). It targets industrial PLCs, motion controllers, and networked HMI systems requiring real-time deterministic control and secure connectivity.
For engineers reviewing the R5F572NDDGFC#V0 datasheet, R5F572NDDGFC#V0 pinout, R5F572NDDGFC#V0 application, or R5F572NDDGFC#V0 equivalent, key selection criteria include its 224-pin LFBGA package, 240 MHz CPU clock, dual-bank flash architecture, IEEE 1588-capable Ethernet MAC, and integrated CAN FD transceiver - all critical for deterministic industrial networking and functional safety–aware designs.
Technical Context
The R5F572NDDGFC#V0 implements the RXv3 CPU core with 6-stage superscalar pipeline, supporting both little-endian and big-endian operation via software-configurable mode. Its system architecture integrates a multi-layer AXI bus matrix enabling concurrent access to flash, SRAM, and peripherals without contention.
Real-time performance is enhanced by the on-chip CMT (Compare Match Timer), GPT (General PWM Timer) with 32-bit resolution and dead-time insertion, and a dedicated interrupt controller supporting 256 priority levels with fast vectoring. The device includes a hardware-based memory protection unit (MPU) with 16 regions and configurable access attributes for task isolation in RTOS environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit superscalar core, 240 MHz max - enables high-throughput deterministic control loops and multitasking in industrial automation. |
| Flash Memory | 4 MB dual-bank flash with SWAP function - allows seamless firmware updates without halting real-time operation. |
| SRAM | 1 MB on-chip SRAM (including 64 KB TCM) - provides low-latency data access for time-critical ISR and control algorithms. |
| Ethernet Interface | IEEE 802.3-compliant MAC with IEEE 1588 v2 hardware timestamping - supports precise time-synchronized industrial Ethernet protocols (e.g., EtherCAT slave, PROFINET IRT). |
| CAN Interface | CAN FD controller + integrated transceiver (ISO 11898-2 compliant) - enables high-speed fieldbus communication up to 5 Mbps with extended data frames. |
| Security Features | AES-128/256, SHA-1/256, RSA-2048, TRNG, and secure boot ROM - delivers root-of-trust for firmware authentication and encrypted data handling. |
| Package | 224-pin LFBGA (15 mm × 15 mm, 0.8 mm pitch) - optimized for high-density industrial PCB layouts with thermal pad for enhanced heat dissipation. |
Pinout & Package
The R5F572NDDGFC#V0 is housed in a 224-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA) package with exposed thermal pad, designed for industrial temperature range (−40°C to +105°C) and reflow-compatible assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Dedicated analog/digital power domains with separate pins per bank - enables noise isolation for ADC, USB, and Ethernet PHY sections. |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3 MII management signals - used for PHY register configuration and link status monitoring. |
| ETH_TXD0–3 / ETH_RXD0–3 | Ethernet data lanes | 4-bit nibble-mode RMII/MII interface - supports 10/100 Mbps operation with optional external PHY or direct connection to compatible PHYs. |
| CANFD0_TX / CANFD0_RX | CAN FD transceiver I/O | Integrated differential CAN FD bus interface - eliminates need for external transceiver in basic node applications. |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 physical layer | Full-speed/high-speed USB 2.0 interface with internal PHY - supports device/host/OTG modes with battery charging detection. |
| CLKIN / CLKOUT | External clock input/output | Supports crystal (1–20 MHz) or external oscillator input - feeds PLL for generating 240 MHz system clock with low-jitter timing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with SWAP | Enables zero-downtime firmware updates by switching active bank during runtime - critical for unattended industrial equipment. |
| Hardware MPU with 16 regions | Provides memory access control per task or privilege level - supports IEC 61508 SIL2/SIL3 partitioning in safety-critical firmware. |
| IEEE 1588 v2 hardware timestamping | Sub-microsecond precision timestamping on Ethernet frames - essential for time-sensitive networking (TSN) and synchronized motion control. |
| Integrated CAN FD transceiver | Reduces BOM count and board space by eliminating external transceiver - simplifies design of compact distributed I/O nodes. |
| Secure boot with ROM-based loader | Verifies digital signature of boot image using embedded public key - prevents unauthorized or corrupted firmware execution at power-on. |
Applications
| Industrial PLC Controller | Networked HMI Terminal |
|---|---|
Use Scenario: Standalone programmable logic controller executing ladder logic and motion control sequences in factory automation cells. IC Role / Device Role / Timing Role: Main system controller managing I/O scanning, PID loop execution, EtherCAT slave communication, and human-machine interaction via local display. Use Value: Dual-bank flash enables remote firmware upgrades without stopping production; 240 MHz CPU ensures sub-millisecond scan times for 100+ I/O points. | Use Scenario: Touch-enabled operator terminal with web server, local data logging, and real-time alarm visualization in packaging machinery. IC Role / Device Role / Timing Role: Application processor running lightweight Linux or FreeRTOS, driving LCD, handling USB storage, and serving HTTP pages over Ethernet. Use Value: Integrated Ethernet MAC with 1588 support enables synchronized alarm timestamps across multiple HMIs; 1 MB SRAM accommodates graphics buffer and web stack. |
| Motion Control Drive | Secure Edge Gateway |
Use Scenario: Servo drive controlling PMSM motors with field-oriented control (FOC) and position feedback via EnDat or BiSS-C encoders. IC Role / Device Role / Timing Role: Real-time motor control MCU coordinating PWM generation, current sensing ADC, encoder interface, and CAN FD command reception. Use Value: GPT timers with dead-time control and encoder quadrature input support enable precise FOC execution; CAN FD allows 5 Mbps command streaming from master controller. | Use Scenario: Industrial edge device aggregating sensor data from Modbus RTU/ASCII networks and forwarding securely to cloud via TLS-encrypted MQTT over Ethernet. IC Role / Device Role / Timing Role: Secure gateway processor performing protocol translation, data encryption, certificate management, and watchdog-monitored network stack. Use Value: Hardware AES/SHA accelerators reduce TLS handshake latency by >70%; secure boot ensures only signed firmware runs, preventing persistent malware injection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MNDGFC#V0 | Same RX72N Group, identical 224-pin LFBGA package, but with 2 MB flash and 512 KB SRAM - no dual-bank flash or IEEE 1588 support. | Suitable for cost-sensitive motion controllers without firmware update requirements or time-synchronized networking. | Select when full 4 MB flash and 1588 timestamping are unnecessary; reduces code density overhead and BOM cost. |
| R5F566TKEDFP#30 | RX66T Group part in 144-pin LFQFP; 1.5 MB flash, 384 KB RAM, no Ethernet MAC or CAN FD transceiver - requires external PHY and transceiver. | Targeted at single-axis servo drives where Ethernet is not required and space constraints favor QFP over BGA. | Choose for simpler, lower-pin-count designs where external Ethernet/CAN components are acceptable and thermal management favors QFP. |
Compared with R5F572NDDGFC#V0, the R5F572MNDGFC#V0 offers reduced memory and feature set at lower cost, while the R5F566TKEDFP#30 trades integration and package complexity for footprint flexibility and lower component count in non-networked applications.
Availability
R5F572NDDGFC#V0 is available at Aetrix Electronics and suitable for industrial PLCs, motion control drives, networked HMIs, and secure edge gateways requiring stable component supply across multi-year production cycles.
Supply support for R5F572NDDGFC#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX72N Group, including the R5F572NDDGFC#V0, was designed specifically for real-time industrial automation applications demanding high-performance deterministic control, integrated industrial networking (Ethernet, CAN FD), and hardware security for firmware integrity and data confidentiality.
FAQ
What is the maximum operating frequency of the R5F572NDDGFC#V0?
The R5F572NDDGFC#V0 operates at a maximum CPU clock frequency of 240 MHz, achieved via its on-chip PLL with support for external crystal (1–20 MHz) or oscillator input. This frequency is sustained across the full industrial temperature range (−40°C to +105°C) under specified voltage conditions, enabling high-speed deterministic execution of control algorithms and protocol stacks in the R5F572NDDGFC#V0.
Does the R5F572NDDGFC#V0 include an integrated Ethernet PHY?
No, the R5F572NDDGFC#V0 integrates only the Ethernet MAC layer compliant with IEEE 802.3 and includes hardware support for IEEE 1588 v2 timestamping. An external PHY IC is required for physical layer signaling. The R5F572NDDGFC#V0 provides MII/RMII interfaces and associated control signals (ETH_MDC, ETH_MDIO, ETH_TXD/ETH_RXD) to connect to standard 10/100 Mbps PHY devices.
What security features are implemented in hardware on the R5F572NDDGFC#V0?
The R5F572NDDGFC#V0 includes dedicated hardware accelerators for AES-128/256 encryption/decryption, SHA-1/256 hashing, RSA-2048 signature verification, and a true random number generator (TRNG). It also features a secure boot ROM that validates digital signatures of the boot image using embedded public keys, ensuring only authenticated firmware executes on the R5F572NDDGFC#V0.
Is the R5F572NDDGFC#V0 pin-compatible with other RX72N Group devices?
Yes, the R5F572NDDGFC#V0 in the 224-pin LFBGA package shares identical pinout with other RX72N Group members in the same package variant (e.g., R5F572MNDGFC#V0, R5F572NNDGFC#V0), enabling hardware reuse across different memory and feature configurations. Pin compatibility is confirmed in Renesas' RX72N Group User's Manual: Hardware, Section 1.5.1 and 1.6.1.
What development tools support the R5F572NDDGFC#V0?
The R5F572NDDGFC#V0 is supported by Renesas' e2 studio IDE, CS+ (formerly CubeSuite+), and IAR Embedded Workbench for RX. Hardware evaluation is enabled via the RX72N Evaluation Board (YRDKRX72N) and the Renesas Starter Kit+ for RX72N (RTK0EG0020S01000BJ), both providing debug interfaces, Ethernet, USB, and expansion headers compatible with the R5F572NDDGFC#V0's peripheral set.
R5F572NDDGFC#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NDDGFC#V0 FAQ
1.How can I place an order for R5F572NDDGFC#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NDDGFC#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NDDGFC#V0 reliable?
The price and inventory of R5F572NDDGFC#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NDDGFC#V0 is usually 5 days.
3.What payment methods are accepted for R5F572NDDGFC#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NDDGFC#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F572NDDGFC#V0?
R5F572NDDGFC#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NDDGFC#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NDDGFC#V0?
For technical support, including R5F572NDDGFC#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NDDGFC#V0 requirements.
6.How does Aetrix verify that R5F572NDDGFC#V0 is sourced from the original manufacturer or authorized distributors?
All R5F572NDDGFC#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NDDGFC#V0 meets industry standards.
7.What is the process for return or replacement of R5F572NDDGFC#V0?
All R5F572NDDGFC#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NDDGFC#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NDDGFC#V0 part is unused and in its original packaging.
Return procedure for R5F572NDDGFC#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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