Renesas R5F572NDDGFP#10
- Part No.:
- R5F572NDDGFP#10
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R5F572NDDGFP#10.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 100LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,153
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F572NDDGFP#10 from Renesas Electronics is a 32-bit RXv3 core microcontroller in the RX72N Group, featuring 1024 KB flash, 512 KB SRAM, and integrated Ethernet MAC with IEEE 1588 support. It operates at up to 240 MHz, includes dual CAN FD controllers, USB 2.0 FS/HS, and supports industrial real-time control in motion systems and PLCs.
For engineers reviewing the R5F572NDDGFP#10 datasheet, R5F572NDDGFP#10 pinout, R5F572NDDGFP#10 application, or R5F572NDDGFP#10 equivalent, key selection criteria include Ethernet timing precision (IEEE 1588 hardware timestamping), dual CAN FD bandwidth allocation, SRAM retention during low-power modes, and QFP-144 pin compatibility with legacy RX72N designs.
Technical Context
The R5F572NDDGFP#10 implements the RXv3 CPU core with 240 MHz max frequency, 6-stage superscalar pipeline, and hardware FPU supporting single/double-precision IEEE 754 arithmetic. It integrates a 32-bit bus matrix with AXI/AHB bridges enabling concurrent access to flash, SRAM, and peripherals without arbitration stalls.
Its system architecture includes a dedicated real-time OS timer (RTT), 24-channel event link controller (ELC) for peripheral synchronization, and a security engine with AES-128/256, SHA-256, and TRNG - all accessible via secure boot ROM with immutable public key verification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit superscalar core, 240 MHz max - enables deterministic <1 µs interrupt latency for motion control loops |
| Memory | 1024 KB on-chip flash (with ECC), 512 KB SRAM (with parity) - supports dual-bank flash for zero-downtime firmware updates |
| Ethernet | 10/100 Mbps MAC with IEEE 1588 v2 hardware timestamping - achieves ±50 ns time sync accuracy in TSN networks |
| CAN FD | Dual CAN FD controllers (ISO 11898-1:2015), up to 8 Mbps data phase - allows high-bandwidth sensor fusion in automotive ECUs |
| USB | USB 2.0 HS/FS device/host/OTG with PHY - enables field-upgradeable firmware via mass storage class without external transceiver |
| Security | Hardware AES-128/256, SHA-256, TRNG, and secure boot ROM - enforces chain-of-trust from reset vector to application code |
| Package | 144-pin LFQFP (20 × 20 mm, 0.5 mm pitch) - compatible with standard reflow profiles and automated optical inspection |
Pinout & Package
144-pin Low-Profile Quad Flat Package (LFQFP), 20 mm × 20 mm body, 0.5 mm lead pitch, exposed thermal pad (EP), RoHS-compliant matte tin finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply and ground | Separate analog/digital domains with dedicated decoupling pads - ensures <10 mV ripple under 200 mA dynamic load |
| CLKIN, EXTAL, XTAL | External clock input/output | Supports 1–20 MHz crystal or CMOS clock source - enables precise PLL lock with ±0.1% frequency stability over -40°C to +85°C |
| ETH_MDC, ETH_MDIO | MDIO management interface | Configures external PHY registers at 2.5 MHz max - eliminates need for software bit-banging in Ethernet initialization |
| CAN0_TX, CAN0_RX | CAN FD channel 0 differential I/O | 5 V-tolerant inputs with slew-rate control - meets ISO 11898-2 EMC requirements without external termination resistors |
| USB_VBUS, USB_DP, USB_DM | USB 2.0 physical layer | Integrated transceiver with VBUS detection - supports host negotiation and battery charging detection per USB BC 1.2 |
| RESET | Active-low reset input | Debounced internally with 10 ms timeout - prevents spurious resets during power ramp-up or ESD events |
Key Features
| Feature | Design Value |
|---|---|
| Real-time Ethernet | Hardware-accelerated IEEE 1588 timestamping with sub-100 ns resolution - enables synchronized multi-axis motion control across distributed drives |
| Dual CAN FD | Independent message RAM with configurable FIFO depth (up to 128 entries per channel) - supports mixed legacy CAN 2.0B and CAN FD frames without CPU intervention |
| Secure Boot | Immutable ROM bootloader verifying SHA-256 hash of signed firmware image - blocks unauthorized code execution before first instruction fetch |
| Event Link Controller | 24-channel hardware event router with programmable priority and delay - replaces software polling for ADC-triggered PWM updates in servo loops |
| Low-Power Modes | Seven power states including Deep Software Standby (0.3 µA) with SRAM retention - extends battery life in wireless HMI nodes without losing context |
Applications
| Industrial PLC | Motion Control Drive |
|---|---|
Use Scenario: Modular programmable logic controller with distributed I/O over EtherCAT. IC Role / Device Role / Timing Role: Main controller executing IEC 61131-3 logic with deterministic cycle times and synchronized axis commands. Use Value: IEEE 1588 hardware timestamping ensures <1 µs jitter between master and slave nodes, meeting IEC 61784-2 Class A timing requirements. | Use Scenario: Servo drive with position/velocity/torque loop closure and field-oriented control. IC Role / Device Role / Timing Role: Real-time executor of FOC algorithms and encoder interface manager with 100 kHz PWM generation. Use Value: Dual CAN FD handles motor feedback and safety signals simultaneously at 5 Mbps, reducing wiring complexity versus discrete RS-485 networks. |
| Smart Gateway | Factory HMI |
Use Scenario: Protocol translator bridging Modbus RTU, CANopen, and MQTT over Wi-Fi/Ethernet. IC Role / Device Role / Timing Role: Secure edge node aggregating and preprocessing sensor data before cloud upload. Use Value: Hardware AES-256 encrypts telemetry payloads before transmission, satisfying GDPR and NIST SP 800-171 encryption mandates. | Use Scenario: Touch-based operator interface with local alarm logging and remote diagnostics. IC Role / Device Role / Timing Role: Graphics controller driving 800×480 LCD with capacitive touch overlay and audio feedback. Use Value: 512 KB SRAM buffers full screen frame buffer and touch gesture history, eliminating external SDRAM and reducing BOM cost by $1.20/unit. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MNDGFP#10 | Same RX72N family, 512 KB flash / 256 KB SRAM - halved memory capacity | Suitable for cost-sensitive HMI or gateway nodes without complex protocol stacks | Select when firmware size <384 KB and no dual CAN FD or Ethernet required |
| R5F566TEADFP#30 | RX66T family, 240 MHz, 1 MB flash, no Ethernet MAC or IEEE 1588 support | Optimized for motor control with 32-channel PWM and advanced timer synchronization | Select for pure motor drive applications where network connectivity is handled externally |
Compared with R5F572MNDGFP#10 and R5F566TEADFP#30, the R5F572NDDGFP#10 uniquely combines industrial Ethernet, dual CAN FD, and large on-chip memory in a single 144-pin QFP - making it the only option for space-constrained, networked real-time controllers requiring both deterministic comms and local processing.
Availability
R5F572NDDGFP#10 is available at Aetrix Electronics and suitable for industrial automation, motion control, and smart gateway applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F572NDDGFP#10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX72N Group, including the R5F572NDDGFP#10, was designed specifically for real-time industrial networking applications - integrating Ethernet, CAN FD, and security features to replace multi-chip solutions in PLCs, drives, and gateways.
FAQ
What is the maximum operating frequency of the R5F572NDDGFP#10?
The R5F572NDDGFP#10 operates at a maximum CPU frequency of 240 MHz, achieved via its on-chip PLL with fractional divider. This frequency is guaranteed across the full industrial temperature range (-40°C to +85°C) when supplied with 3.3 V ±10% and using the recommended external 8 MHz crystal. The R5F572NDDGFP#10 maintains this speed with zero wait-state access to on-chip flash due to its 6-stage superscalar pipeline and 32 KB instruction cache.
Does the R5F572NDDGFP#10 support IEEE 1588 Precision Time Protocol?
Yes, the R5F572NDDGFP#10 includes a hardware IEEE 1588 v2 PTP engine with nanosecond-resolution timestamping on both transmit and receive Ethernet frames. It supports all mandatory PTP profiles including Default Profile and Power Profile, and provides dedicated registers for correction field adjustment and clock servo control - enabling sub-microsecond time synchronization without CPU overhead. This capability is integral to the R5F572NDDGFP#10's Ethernet MAC block.
What package type and pin count does the R5F572NDDGFP#10 use?
The R5F572NDDGFP#10 uses a 144-pin Low-Profile Quad Flat Package (LFQFP) with 20 mm × 20 mm body size and 0.5 mm lead pitch. This package includes an exposed thermal pad for enhanced heat dissipation and is compatible with standard JEDEC J-STD-020 reflow profiles. Pin assignments match the RX72N Group's 144-pin LFQFP footprint, ensuring mechanical and layout compatibility with existing R5F572N-series designs.
How much on-chip memory does the R5F572NDDGFP#10 provide?
The R5F572NDDGFP#10 integrates 1024 KB of on-chip flash memory with ECC protection and 512 KB of SRAM with parity checking. Flash memory is organized in dual banks to support background read-while-write operations, while SRAM includes retention capability in low-power modes. These memory resources are directly accessible via the R5F572NDDGFP#10's 32-bit AXI bus matrix, delivering sustained bandwidth up to 480 MB/s for real-time data buffering and protocol stack execution.
What security features are implemented in hardware on the R5F572NDDGFP#10?
The R5F572NDDGFP#10 includes a dedicated security engine with hardware-accelerated AES-128/256, SHA-256, and true random number generation (TRNG). It boots exclusively from immutable ROM containing a public-key verifier for signed firmware images. All cryptographic operations occur in isolated secure memory regions, and debug access is permanently disabled after secure provisioning. These features are physically embedded in the R5F572NDDGFP#10 die and require no external components to enforce secure boot or runtime encryption.
R5F572NDDGFP#10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 78
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 22x12b; D/A 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NDDGFP#10 FAQ
1.How can I place an order for R5F572NDDGFP#10 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NDDGFP#10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NDDGFP#10 reliable?
The price and inventory of R5F572NDDGFP#10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NDDGFP#10 is usually 5 days.
3.What payment methods are accepted for R5F572NDDGFP#10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NDDGFP#10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F572NDDGFP#10?
R5F572NDDGFP#10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NDDGFP#10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NDDGFP#10?
For technical support, including R5F572NDDGFP#10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NDDGFP#10 requirements.
6.How does Aetrix verify that R5F572NDDGFP#10 is sourced from the original manufacturer or authorized distributors?
All R5F572NDDGFP#10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NDDGFP#10 meets industry standards.
7.What is the process for return or replacement of R5F572NDDGFP#10?
All R5F572NDDGFP#10 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NDDGFP#10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NDDGFP#10 part is unused and in its original packaging.
Return procedure for R5F572NDDGFP#10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F572NDDGFP#10 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

