Renesas R5F572NDDGLK#20
- Part No.:
- R5F572NDDGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F572NDDGLK#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
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Product details
Overview
R5F572NDDGLK#20 from Renesas Electronics is a 32-bit RXv3 core microcontroller in the RX72N Group, featuring 4 MB flash memory, 1 MB SRAM, dual CAN FD interfaces, and integrated Ethernet MAC with IEEE 1588 support - deployed in industrial PLCs for deterministic motion control and real-time I/O synchronization.
For engineers reviewing the R5F572NDDGLK#20 datasheet, R5F572NDDGLK#20 pinout, R5F572NDDGLK#20 application, or R5F572NDDGLK#20 equivalent, key selection criteria include its 224-pin LFBGA package, 240 MHz max CPU frequency, hardware-accelerated AES/SHA crypto engine, and support for TSN (Time-Sensitive Networking) via integrated Ethernet PHY interface timing control.
Technical Context
The R5F572NDDGLK#20 implements the RXv3 CPU core with 240 MHz operation, 6-stage superscalar pipeline, and dual-issue capability. It integrates a 32-channel event link controller (ELC) for zero-cycle peripheral triggering and a 24-channel DMAC with scatter-gather support for high-throughput data movement between peripherals and memory.
Its system architecture includes a multi-layer AXI bus matrix, dedicated instruction and data caches (32 KB each), and memory protection unit (MPU) with 16 regions. The device supports simultaneous execution of real-time control tasks (via GPTP timer and PWM units) and communication stacks (CAN FD + Ethernet TCP/IP) without resource contention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit superscalar core, 240 MHz max - enables sub-1 µs interrupt latency and deterministic real-time task scheduling. |
| Flash Memory | 4 MB on-chip flash with ECC and background operation - supports live firmware updates without halting control loops. |
| SRAM | 1 MB on-chip SRAM with parity/ECC - accommodates large real-time buffers and safety-critical data structures. |
| Communication | Dual CAN FD (up to 5 Mbps) + 10/100 Mbps Ethernet MAC with IEEE 1588 v2 hardware timestamping - enables synchronized distributed I/O in industrial networks. |
| Crypto Acceleration | Hardware AES-128/256, SHA-256, TRNG - accelerates secure boot, OTA authentication, and encrypted fieldbus communication. |
| Package | 224-pin LFBGA (15 mm × 15 mm, 0.8 mm pitch) - optimized for high-density industrial PCB layouts with thermal pad for enhanced heat dissipation. |
| Operating Temp | −40°C to +105°C (Industrial grade) - qualified for use in cabinet-mounted PLCs and motor drive controllers. |
Pinout & Package
224-pin LFBGA (15 mm × 15 mm, 0.8 mm pitch) with exposed thermal pad (EPAD). Package meets JEDEC MO-276AA standard and supports reflow soldering per J-STD-020D.3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Core power supply | 1.25 V ±3% for CPU/SRAM; requires low-noise regulation and local decoupling for stable 240 MHz operation. |
| VCCIO0–VCCIO3 | I/O bank supplies | Configurable 1.8 V / 2.5 V / 3.3 V per bank - enables mixed-voltage interfacing with sensors, FPGAs, and legacy fieldbus transceivers. |
| ETH_MDC/MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO bus for PHY configuration - supports auto-negotiation and link status monitoring without CPU overhead. |
| CAN0_TX/CAN0_RX | CAN FD channel 0 differential pair | High-speed (up to 5 Mbps) or fault-tolerant mode - connects directly to ISO 11898-2/3 compliant transceivers for automotive-grade diagnostics. |
| CLKIN | External clock input | Accepts 1–20 MHz crystal or CMOS clock - feeds PLL for precise 240 MHz system clock generation with <±50 ppm stability. |
| RESET | Active-low reset input | Asynchronous, glitch-filtered reset assertion - ensures reliable recovery from brown-out or watchdog timeout events. |
Key Features
| Feature | Design Value |
|---|---|
| TSN Timing Control | Hardware timestamping, gate control list (GCL), and scheduled traffic shaping for IEEE 802.1Qbv - enables sub-1 µs time synchronization across Ethernet nodes. |
| GPTP Timer | 24-bit general-purpose timer with quadrature encoder input and complementary PWM output - supports servo motor position/velocity feedback and dead-time insertion. |
| Event Link Controller (ELC) | 32-event source routing to 24 peripherals without CPU intervention - eliminates ISR latency for sensor-triggered ADC sampling or PWM update. |
| Safety Support | Lockstep CPU core option, BIST for flash/SRAM, and error-correcting code (ECC) on all memories - meets IEC 61508 SIL2 requirements for functional safety applications. |
| Secure Boot | ROM-based bootloader with public-key verification (RSA-2048) and hash-based firmware image validation - prevents unauthorized firmware execution at power-on. |
Applications
| Industrial PLC | Robot Motion Controller |
|---|---|
Use Scenario: Central logic unit in modular programmable logic controllers handling analog I/O, motion profiling, and fieldbus gateway functions. IC Role / Device Role / Timing Role: Real-time execution host for IEC 61131-3 ladder logic and motion control algorithms, synchronized via EtherCAT or PROFINET. Use Value: Dual CAN FD + Ethernet TSN enables deterministic cycle times (<1 ms) and precise axis coordination across distributed I/O modules. | Use Scenario: Embedded controller in collaborative robot joints managing torque sensing, motor commutation, and safety monitoring. IC Role / Device Role / Timing Role: Safety-certified motion processor executing trajectory planning, current loop control, and STO/SS1 safety functions. Use Value: Lockstep CPU and ECC memory ensure SIL2 compliance while hardware crypto secures firmware updates over wireless maintenance links. |
| Smart Power Inverter | IIoT Edge Gateway |
Use Scenario: High-efficiency variable-frequency drive controlling induction or PMSM motors in HVAC and pump systems. IC Role / Device Role / Timing Role: Field-oriented control (FOC) engine with PWM generation, ADC sampling, and thermal monitoring. Use Value: 240 MHz CPU and ELC enable 20 kHz PWM switching with <500 ns jitter, improving motor efficiency and reducing audible noise. | Use Scenario: Protocol-agnostic edge node aggregating Modbus RTU, CANopen, and OPC UA data for cloud telemetry. IC Role / Device Role / Timing Role: Secure protocol translation hub with TLS 1.2 offload and time-stamped event logging. Use Value: Hardware AES/SHA accelerates certificate-based authentication and encrypted payload transmission without degrading real-time polling performance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MDDGLK#20 | Same RX72N Group, 2 MB flash / 512 KB SRAM - no Ethernet MAC or TSN support. | Limited to CAN-only industrial controllers without time-synchronized networking. | Select when Ethernet connectivity and IEEE 1588 timing are not required; lower cost and reduced BOM complexity. |
| R5F566TEBDFP#30 | RX66T Group, 1.25 MB flash / 192 KB SRAM, 160 MHz, no Ethernet, single CAN FD. | Optimized for motor control only - lacks industrial networking peripherals and large memory footprint. | Prefer for cost-sensitive servo drives where motion control is primary and network integration is external. |
Compared with R5F572MDDGLK#20 and R5F566TEBDFP#30, the R5F572NDDGLK#20 uniquely combines full TSN-capable Ethernet, dual CAN FD, and 4 MB flash in a single industrial-grade MCU - making it the only choice for next-generation distributed control systems requiring synchronized real-time communication and local intelligence.
Availability
R5F572NDDGLK#20 is available at Aetrix Electronics and suitable for industrial automation, robotics, and smart energy applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F572NDDGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX72N Group - including the R5F572NDDGLK#20 - was designed specifically for industrial automation systems requiring real-time determinism, functional safety, and converged IT/OT networking capabilities.
FAQ
What is the maximum operating frequency of the R5F572NDDGLK#20?
The R5F572NDDGLK#20 operates at a maximum CPU frequency of 240 MHz using its on-chip PLL with external crystal input. This frequency is fully supported across the entire industrial temperature range (−40°C to +105°C) and enables sub-microsecond interrupt response for hard real-time control tasks. The R5F572NDDGLK#20 achieves this performance with a 6-stage superscalar pipeline and dual-issue execution capability.
Does the R5F572NDDGLK#20 support IEEE 1588 Precision Time Protocol?
Yes, the R5F572NDDGLK#20 includes hardware timestamping logic within its integrated Ethernet MAC that fully complies with IEEE 1588-2008 (v2) for both one-step and two-step clock synchronization. The R5F572NDDGLK#20 supports hardware-assisted PTP message processing, enabling sub-100 ns timestamp accuracy and deterministic delay measurement - critical for TSN-based industrial networks.
What safety certifications does the R5F572NDDGLK#20 target?
The R5F572NDDGLK#20 is designed to support IEC 61508 SIL2 and ISO 13849 PL d functional safety requirements. It includes lockstep CPU core option, memory BIST, ECC on flash/SRAM, and diagnostic libraries provided by Renesas. While the R5F572NDDGLK#20 itself is not pre-certified, its integrated safety features enable certified system-level implementations when used with Renesas' safety manual and FMEDA data.
Can the R5F572NDDGLK#20 execute secure boot from external QSPI flash?
No - the R5F572NDDGLK#20 performs secure boot exclusively from its internal 4 MB flash memory using ROM-based bootloader with RSA-2048 signature verification. External QSPI flash can be used for secondary firmware storage or data logging, but the initial boot image must reside in on-chip flash and be cryptographically validated before execution. This design ensures tamper-resistant root-of-trust for the R5F572NDDGLK#20.
What development tools are officially supported for the R5F572NDDGLK#20?
Renesas provides full toolchain support for the R5F572NDDGLK#20 including e2 studio IDE, CS+ compiler, and Renesas Flash Programmer. Hardware debugging is enabled via SWD/JTAG using E2 Lite or E2 emulator. The R5F572NDDGLK#20 is also supported by Renesas' Flexible Software Package (FSP) v4.x with drivers for Ethernet, CAN FD, USB, and safety libraries - all validated for use with the R5F572NDDGLK#20.
R5F572NDDGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NDDGLK#20 FAQ
1.How can I place an order for R5F572NDDGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NDDGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NDDGLK#20 reliable?
The price and inventory of R5F572NDDGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NDDGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F572NDDGLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NDDGLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F572NDDGLK#20?
R5F572NDDGLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NDDGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NDDGLK#20?
For technical support, including R5F572NDDGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NDDGLK#20 requirements.
6.How does Aetrix verify that R5F572NDDGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NDDGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NDDGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F572NDDGLK#20?
All R5F572NDDGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NDDGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NDDGLK#20 part is unused and in its original packaging.
Return procedure for R5F572NDDGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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