Renesas R5F572NDHDLK#20
- Part No.:
- R5F572NDHDLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F572NDHDLK#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

Inventory:416
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Product details
Overview
R5F572NDHDLK#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 240 MHz, featuring double-precision IEEE-754 FPU, 4 MB on-chip code flash, 1 MB SRAM (including 32 KB ECC RAM), and integrated Ethernet MAC compliant with IEEE 1588. It supports CAN (3 channels), USB 2.0 FS host/function, SDHI, QSPI, and GLCDC - deployed in industrial HMIs, motor control gateways, and networked edge devices requiring deterministic real-time performance.
For engineers reviewing the R5F572NDHDLK#20 datasheet, R5F572NDHDLK#20 pinout, R5F572NDHDLK#20 application, or R5F572NDHDLK#20 equivalent, key selection criteria include IEEE 1588 PTP timing accuracy, dual-bank flash for safe firmware updates, 182 GPIOs with 5-V tolerance, and hardware-accelerated trigonometric (TFU) and encryption (TSIP/AES) functions - all within a 176-pin LFBGA package rated for –40°C to +105°C.
Technical Context
The R5F572NDHDLK#20 implements the RXv3 CPU core with 16 general-purpose 32-bit registers, double-precision FPU (16×64-bit data registers), and collective register bank save for fast context switching. Its clock system includes PLLs for ICLK (240 MHz), PCLKA (120 MHz), and PCLKB (60 MHz), enabling independent domain scaling for CPU, Ethernet/USB peripherals, and timers/ADCs.
Memory architecture comprises 4 MB dual-bank code flash (no-wait ≤120 MHz), 32 KB data flash (100k erase cycles), 1 MB SRAM split into 512 KB high-speed RAM and 512 KB expansion RAM, plus 32 KB ECC RAM and 8 KB standby RAM. Peripheral interconnect uses ELC (Event Link Controller) to route 135 internal event signals - eliminating CPU intervention for timer-triggered ADC starts or PWM dead-time compensation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 240 MHz max - delivers 1396 CoreMark; supports little/big-endian data, 113 instructions including DSP and FP ops. |
| Flash Memory | 4 MB dual-bank code flash - enables background programming and safe bank-swapping during runtime firmware updates. |
| RAM | 1 MB total: 512 KB no-wait SRAM (≤120 MHz), 512 KB expansion RAM, 32 KB ECC RAM (SEC-DED), 8 KB battery-backed standby RAM. |
| Connectivity | Ethernet MAC ×2 (IEEE 1588 PTP), CAN ×3 (32 mailboxes/channel), USB 2.0 FS host/function, SDHI, QSPI, 3×RSPI, 3×I²C, 13×SCI. |
| Analog Peripherals | Two 12-bit ADCs (8+21 channels), 2×12-bit DACs, on-chip temperature sensor, self-diagnostic A/D disconnection detection. |
| Timers & PWM | GPTW ×4 (32-bit), MTU3a ×9 (16/32-bit), TPUa ×6, CMT/CMTW, PPG - support complementary PWM, phase counting, and dead-time generation for 3-phase inverters. |
| Security & Math | Trusted Secure IP (TSIP), AES-128/192/256, arithmetic unit for sine/cosine/arctangent - hardware-accelerated real-time control math. |
Pinout & Package
Package: PLQP0176KB-C (176-pin LFBGA, 24 mm × 24 mm, 0.5 mm pitch), rated for –40°C to +105°C (G-version).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Core & analog power supply | 2.7–3.6 V operation; separate analog domains enable noise-isolated ADC reference. |
| VBATT | Battery backup supply | Retains RTC operation during main power loss - critical for time-stamped industrial logging. |
| RES# | Active-low reset input | Hardware reset assertion; combined with POR and LVD for robust power sequencing. |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external resonator for precise system clock and IEEE 1588 timestamping. |
| MD0 / MD1 | Mode setting pins | Select single-chip, SCI/USB/FINE boot modes - defines startup behavior and debug interface availability. |
| ETXD0–ETXD3 / ERXD0–ERXD3 | Ethernet PHY data lines | RMII/MII interface pins - enable direct connection to external PHY without external glue logic. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol (PTP) | Hardware timestamping in ETHERC/EPTPC enables sub-microsecond synchronization across industrial Ethernet networks. |
| Dual-bank flash memory | Allows seamless firmware update: execute from Bank A while programming Bank B, then switch on reset - zero downtime. |
| Event Link Controller (ELC) | Routes 135 internal events (e.g., timer overflow → ADC start) without CPU involvement - reduces latency and ISR load. |
| Trigonometric Function Unit (TFU) | Hardware acceleration for sin/cos/atan - cuts motor control loop computation time vs. software libraries by >90%. |
| Trusted Secure IP (TSIP) | On-die cryptographic engine supporting AES and secure key storage - meets IEC 60730 Class B functional safety requirements. |
Applications
| Industrial HMI Gateway | Networked Motor Drive Controller |
|---|---|
|
Use Scenario: Central gateway aggregating Modbus RTU from PLCs, converting to EtherNet/IP for SCADA systems. IC Role / Device Role / Timing Role: Real-time protocol translation engine with IEEE 1588-synchronized packet scheduling and dual-CAN bus bridging. Use Value: Eliminates external FPGA or dual-MCU architecture - single-chip solution reduces BOM cost and board area by 40%. |
Use Scenario: Closed-loop servo drive managing three-phase PMSM with field-oriented control (FOC) and safety monitoring. IC Role / Device Role / Timing Role: Real-time motion controller executing FOC algorithm at 20 kHz using TFU and GPTW-complementary PWM outputs. Use Value: Hardware-accelerated trigonometry and dead-time generation ensure <500 ns PWM jitter - critical for torque ripple reduction. |
| Smart Building Edge Node | Medical Infusion Pump Controller |
|
Use Scenario: HVAC zone controller collecting temperature/humidity via I²C sensors, communicating over Ethernet and CAN to building management system. IC Role / Device Role / Timing Role: Secure edge node with TSIP-based firmware authentication and RTC-backed event logging. Use Value: Integrated AES and secure boot prevent unauthorized firmware updates - satisfies UL 60730 Class B compliance. |
Use Scenario: Battery-powered infusion pump requiring precise flow rate control, low-power operation, and fault-safe shutdown. IC Role / Device Role / Timing Role: Safety-critical controller using deep software standby mode (1.2 µA), IWDT windowed timeout, and analog input disconnection detection. Use Value: On-chip 12-bit ADC with self-diagnostic and 8 KB standby RAM preserve therapy state during brownout - ensures patient safety continuity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572NDDFLK#20 | Same RX72N core, but 144-pin LFQFP (PLQP0144KA-B), 2 MB flash, 512 KB SRAM - smaller footprint, lower I/O count (136 pins). | Suitable for space-constrained designs where Ethernet and full CAN count are not required. | Select when PCB area is limited and peripheral count can be reduced - no pin compatibility with R5F572NDHDLK#20. |
| R5F572MDDFLK#20 | RX72M Group variant: identical package/pinout, but lacks IEEE 1588 PTP, GLCDC, DRW2D, and SDHI - optimized for motor control only. | Targeted at cost-sensitive inverter drives without HMI or networked diagnostics. | Choose for pure motor control applications where Ethernet timestamping and graphics are unnecessary - pin-compatible but functionally reduced. |
Compared with R5F572NDHDLK#20, the R5F572NDDFLK#20 trades I/O count and memory for compactness, while the R5F572MDDFLK#20 removes PTP, graphics, and SD interfaces to lower cost - making R5F572NDHDLK#20 the optimal choice for full-featured industrial edge nodes requiring synchronized networking and human-machine interaction.
Availability
R5F572NDHDLK#20 is available at Aetrix Electronics and suitable for industrial HMIs, networked motor controllers, smart building edge nodes, and medical infusion pumps requiring stable component supply across extended product lifecycles.
Supply support for R5F572NDHDLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and IoT applications.
The RX72N Group - including R5F572NDHDLK#20 - was designed for high-integration industrial edge devices requiring real-time Ethernet, functional safety, and rich human-machine interface capabilities.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F572NDHDLK#20?
The R5F572NDHDLK#20 operates at a maximum frequency of 240 MHz and achieves 1396 CoreMark - measured under standard conditions per EEMBC methodology. This performance stems from the RXv3 CPU core's dual-issue capability, 16-register bank, and optimized instruction pipeline. The R5F572NDHDLK#20 sustains this speed across its full voltage range (2.7–3.6 V) with appropriate thermal management.
Does the R5F572NDHDLK#20 support IEEE 1588 Precision Time Protocol, and how is it implemented?
Yes, the R5F572NDHDLK#20 supports IEEE 1588 PTP via its integrated EPTPCb module working in conjunction with the ETHERC Ethernet MAC. Hardware timestamping occurs at the MAC layer with nanosecond resolution, and the PTP engine handles message delay measurement, offset correction, and synchronization to a master clock - all without CPU intervention. This makes the R5F572NDHDLK#20 suitable for time-critical industrial automation networks.
What are the flash and RAM configurations of the R5F572NDHDLK#20?
The R5F572NDHDLK#20 integrates 4 MB of dual-bank code flash memory (enabling background programming and safe bank swapping), 32 KB of reprogrammable data flash (rated for 100,000 erase cycles), 1 MB of SRAM (split into 512 KB high-speed RAM and 512 KB expansion RAM), 32 KB of ECC RAM with SEC-DED protection, and 8 KB of battery-backed standby RAM. All memory blocks are accessible without wait states at their respective maximum clock frequencies.
Which communication interfaces does the R5F572NDHDLK#20 support for industrial networking?
The R5F572NDHDLK#20 supports multiple industrial networking interfaces: dual-channel Ethernet MAC compliant with IEEE 1588, three independent CAN 2.0B controllers (32 mailboxes each), USB 2.0 Full-Speed host/function with OTG, SD host interface (SDHI), and QSPI for serial flash. It also includes 13 serial channels (SCI/SCIi/SCIh), 3 I²C buses (up to 1 Mbps), and 3 RSPI ports - providing flexible connectivity for multi-protocol industrial gateways.
How does the R5F572NDHDLK#20 meet functional safety requirements such as IEC 60730?
The R5F572NDHDLK#20 includes dedicated hardware features for IEC 60730 Class B compliance: oscillation-stoppage detection, CRC accelerators (CRCA), windowed independent watchdog timer (IWDTa), self-diagnostic A/D converter test, register write protection, and memory ECC. These are documented in Renesas' Functional Safety Manual (R01UM0122EJ0200) and enable certified safety firmware development - critical for R5F572NDHDLK#20 deployments in medical and industrial control systems.
R5F572NDHDLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX72N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NDHDLK#20 FAQ
1.How can I place an order for R5F572NDHDLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NDHDLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NDHDLK#20 reliable?
The price and inventory of R5F572NDHDLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NDHDLK#20 is usually 5 days.
3.What payment methods are accepted for R5F572NDHDLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NDHDLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F572NDHDLK#20?
R5F572NDHDLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NDHDLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NDHDLK#20?
For technical support, including R5F572NDHDLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NDHDLK#20 requirements.
6.How does Aetrix verify that R5F572NDHDLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NDHDLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NDHDLK#20 meets industry standards.
7.What is the process for return or replacement of R5F572NDHDLK#20?
All R5F572NDHDLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NDHDLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NDHDLK#20 part is unused and in its original packaging.
Return procedure for R5F572NDHDLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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