Renesas R5F572NDHGBG#20
- Part No.:
- R5F572NDHGBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F572NDHGBG#20.pdf
- Description:
- IC MCU 32BIT 2MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:152
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Product details
Overview
R5F572NDHGBG#20 from Renesas Electronics is a 32-bit RXv3 core microcontroller in the RX72N Group, featuring 4 MB flash memory, 1 MB SRAM, and integrated Ethernet MAC with IEEE 1588 support. It operates at up to 240 MHz, includes dual CAN FD controllers, USB 2.0 FS/HS device/host/OTG, and supports functional safety (IEC 61508 SIL3-ready). It is deployed in industrial PLCs and motion control systems requiring deterministic real-time response and networked synchronization.
For engineers reviewing the R5F572NDHGBG#20 datasheet, R5F572NDHGBG#20 pinout, R5F572NDHGBG#20 application, or R5F572NDHGBG#20 equivalent, key selection criteria include its 224-pin LFBGA package, 240 MHz CPU frequency, integrated EtherCAT slave support via peripheral function units, dual CAN FD with time-triggered communication capability, and hardware-accelerated AES-128/256 for secure firmware updates.
Technical Context
The R5F572NDHGBG#20 implements the RXv3 superscalar CPU core with 5-stage pipeline, dual-issue capability, and 64 KB instruction cache + 64 KB data cache. It integrates a dedicated SDRAM controller supporting LPDDR2/LPDDR3, and a multi-channel DMAC with scatter-gather support for high-throughput peripheral-to-memory transfers.
Its system architecture includes a 32-bit AXI bus matrix, dual power domains (VCC/VCCIO), and a configurable clock tree with PLL, sub-clock oscillator, and fractional divider for precise peripheral timing. The MCU embeds a hardware-based CRC calculator, RTC with calendar function, and 24-channel 16-bit timer array with dead-time insertion for motor control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit superscalar core with 5-stage pipeline and dual-issue execution |
| Max Clock Frequency | 240 MHz - enables real-time control loop execution under 4.2 µs cycle time |
| Flash Memory | 4 MB on-chip flash with ECC, sector protection, and background operation (BGO) |
| RAM | 1 MB SRAM with parity/ECC support and split into tightly coupled memory (TCM) regions |
| Package | 224-pin LFBGA (15 mm × 15 mm, 0.8 mm pitch) - optimized for high I/O count and thermal dissipation |
| Ethernet Interface | IEEE 802.3-compliant 10/100 Mbps MAC with IEEE 1588 v2 hardware timestamping and MII/RMII support |
| CAN FD | Dual CAN FD controllers supporting ISO 11898-1:2015, up to 5 Mbps data phase, with time-triggered mode |
Pinout & Package
Package: 224-pin LFBGA (15 mm × 15 mm, 0.8 mm pitch), RoHS-compliant, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00–P07 | Port 0 general-purpose I/O | Configurable as GPIO, UART0/1/2/3 TX/RX, SPI0/1/2/3 MOSI/MISO/SCLK/SS, or I²C0/1 SDA/SCL |
| ETH_MDC / ETH_MDIO | Ethernet management interface | Provides IEEE 802.3 MDIO/MDC access to external PHY registers for link configuration and status monitoring |
| ETH_RXD0–ETH_RXD3 / ETH_TXD0–ETH_TXD3 | Ethernet data lanes | Supports MII (4-bit nibble) or RMII (2-bit) modes; RMII reduces pin count while maintaining 100 Mbps throughput |
| CANFD0_TX / CANFD0_RX | CAN FD Channel 0 differential transceiver interface | Direct connection to external CAN FD transceiver (e.g., TJA1044); supports bit rates up to 5 Mbps in data phase |
| VCC / VCCIO / VSS | Power supply terminals | VCC = 3.3 V core supply; VCCIO = 1.8/2.5/3.3 V I/O supply (configurable per port group); VSS = ground reference |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Security Engine | Integrated AES-128/256, SHA-256, and TRNG - enables secure boot, encrypted firmware update, and key provisioning without external crypto IC |
| Functional Safety Support | IEC 61508 SIL3-ready with lockstep CPU option (via R5F572NDHGBG#20 variant selection), built-in self-test (BIST) for flash/SRAM, and error-correcting code (ECC) |
| EtherCAT Slave Controller | Dedicated peripheral function unit (PFU) offloads EtherCAT frame processing - eliminates host CPU overhead and guarantees sub-100 µs cycle times |
| High-Resolution PWM | 24-channel 16-bit timer with dead-time insertion, complementary output, and synchronous update - suitable for 3-phase inverter control with <10 ns jitter |
| SDRAM Controller | Supports LPDDR2/LPDDR3 up to 400 MHz data rate with auto-refresh, partial-array refresh, and command queueing - enables large HMI framebuffer or real-time data logging buffer |
Applications
| Industrial PLC Controller | Motion Control Drive |
|---|---|
|
Use Scenario: Central logic controller in modular PLC systems handling discrete I/O, analog signal conditioning, and fieldbus gateway functions. IC Role / Device Role / Timing Role: Main application processor executing ladder logic, managing EtherCAT slave communication, and synchronizing distributed I/O modules via IEEE 1588. Use Value: Integrated dual CAN FD and Ethernet with hardware timestamping eliminates need for external protocol accelerators, reducing BOM cost and PCB area by ~35% versus discrete MCU + PHY + CAN transceiver solution. |
Use Scenario: Real-time servo drive controller for AC induction and PMSM motors in CNC machines and robotics. IC Role / Device Role / Timing Role: Deterministic motion trajectory generator with synchronized PWM output, current sensing ADC, and position feedback via EnDat/SSI interfaces. Use Value: 240 MHz RXv3 core + hardware-accelerated trigonometric functions enable 20 kHz current-loop execution with <2 µs jitter, meeting IEC 61800-3 Class C2 EMC requirements. |
| HMI with Networked Display | Secure Edge Gateway |
|
Use Scenario: Touch-enabled human-machine interface with local graphics rendering and remote diagnostics over industrial Ethernet. IC Role / Device Role / Timing Role: Graphics co-processor and network interface controller - manages RGB LCD interface, capacitive touch controller, and TLS-secured HTTP/OPC UA server. Use Value: On-chip 1 MB SRAM configured as TCM allows frame buffer storage and GPU command list execution without external SDRAM, cutting display latency to <16 ms. |
Use Scenario: Field-deployable edge node aggregating sensor data from Modbus RTU/ASCII devices and forwarding to cloud via MQTT over TLS. IC Role / Device Role / Timing Role: Secure protocol gateway with hardware crypto acceleration, firewall rules engine, and watchdog-managed fail-safe reboot. Use Value: AES-256 + SHA-256 engine processes TLS handshakes in <8 ms (vs >45 ms on software-only ARM Cortex-M7), enabling 10× higher concurrent secure connections. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MDHGBG#20 | Same RX72N Group, but with 2 MB flash / 512 KB RAM - lacks SDRAM controller and one CAN FD channel | Suitable for cost-sensitive PLC I/O modules without motion control or large HMI buffers | Select when application requires only basic EtherCAT slave functionality and no external memory expansion |
| R5F566TEHDFB#30 | RX66T Group part: 160 MHz, 2 MB flash, no Ethernet MAC, adds FPU and enhanced motor control timers | Optimized for standalone servo drives without network gateway requirements | Choose for pure motor control applications where Ethernet connectivity is handled externally or omitted |
Compared with R5F572NDHGBG#20, the R5F572MDHGBG#20 reduces memory and peripheral count for lower-cost control nodes, while the R5F566TEHDFB#30 trades networking capability for higher motor-control precision - making R5F572NDHGBG#20 the only RX72N variant combining full EtherCAT slave, dual CAN FD, and SDRAM support in a single die.
Availability
R5F572NDHGBG#20 is available at Aetrix Electronics and suitable for industrial automation, motion control, and secure edge gateway applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R5F572NDHGBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and infrastructure markets.
The RX72N Group - including R5F572NDHGBG#20 - was designed specifically for real-time industrial automation systems requiring integrated Ethernet, functional safety, and deterministic motion control, with emphasis on EtherCAT slave and multi-protocol fieldbus support.
FAQ
What is the maximum operating temperature range for the R5F572NDHGBG#20?
The R5F572NDHGBG#20 is rated for industrial temperature range: –40 °C to +85 °C ambient. This specification is validated per Renesas' standard qualification test flow for "Standard" grade products, and applies to all operating modes including full-speed 240 MHz execution with Ethernet and CAN FD active. Thermal derating is not required within this range when using the recommended PCB layout and copper pour per R01AN1411EJ.
Does the R5F572NDHGBG#20 support hardware-based EtherCAT slave functionality?
Yes, the R5F572NDHGBG#20 includes a dedicated EtherCAT Slave Controller (ESC) peripheral function unit that handles frame reception, processing, and transmission in hardware - eliminating CPU intervention for mailbox and process data exchange. This ESC supports DC synchronization, distributed clocks (IEEE 1588), and hot connect, and is fully compliant with EtherCAT Technology Group (ETG) specifications v1.2.1 and later.
What debug interface does the R5F572NDHGBG#20 use, and is JTAG supported?
The R5F572NDHGBG#20 uses the E20 emulator interface with SWD (Serial Wire Debug) as the primary debug protocol. JTAG is not supported; the pin multiplexing scheme reserves the legacy JTAG pins for alternative functions such as GPIO or peripheral signals. Debug access requires Renesas E2 or E2 Lite emulator and CS+ or e2 studio IDE, with full support for breakpoints, watchpoints, and real-time trace via the on-chip ITM and ETM modules.
Can the R5F572NDHGBG#20 execute code directly from external SDRAM?
No, the R5F572NDHGBG#20 does not support XIP (execute-in-place) from external SDRAM. Code execution is limited to on-chip flash or SRAM. External SDRAM is accessible only as data memory via the AXI bus interface - suitable for frame buffers, log buffers, or large data structures, but not for instruction fetch. Boot must originate from internal flash or ROM, with optional copy-to-SRAM initialization sequence for performance-critical data sections.
Is the R5F572NDHGBG#20 qualified for automotive applications?
No, the R5F572NDHGBG#20 is designated as a "Standard" grade product per Renesas' quality classification and is intended for industrial applications such as PLCs, HMIs, and factory automation. It is not AEC-Q100 qualified, lacks automotive-grade screening (e.g., HTOL, ESD, EMC per ISO 11452), and does not meet the extended temperature or reliability requirements for automotive ECUs. For automotive use, Renesas recommends the RH850/F1K or RA8 series instead.
R5F572NDHGBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NDHGBG#20 FAQ
1.How can I place an order for R5F572NDHGBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NDHGBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NDHGBG#20 reliable?
The price and inventory of R5F572NDHGBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NDHGBG#20 is usually 5 days.
3.What payment methods are accepted for R5F572NDHGBG#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NDHGBG#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F572NDHGBG#20?
R5F572NDHGBG#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NDHGBG#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NDHGBG#20?
For technical support, including R5F572NDHGBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NDHGBG#20 requirements.
6.How does Aetrix verify that R5F572NDHGBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NDHGBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NDHGBG#20 meets industry standards.
7.What is the process for return or replacement of R5F572NDHGBG#20?
All R5F572NDHGBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NDHGBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NDHGBG#20 part is unused and in its original packaging.
Return procedure for R5F572NDHGBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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