Renesas R5F572NNDGBG#20
- Part No.:
- R5F572NNDGBG#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R5F572NNDGBG#20.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 176LFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F572NNDGBG#20 from Renesas Electronics is a 32-bit RXv3 core microcontroller in the RX72N Group, featuring 4 MB flash memory, 1 MB SRAM, and integrated Ethernet MAC with IEEE 1588 support. It operates at up to 240 MHz, includes dual CAN FD controllers, USB 2.0 FS/HS, and hardware encryption (AES-128/256, SHA, TRNG). It targets industrial PLCs and motion control systems requiring real-time deterministic response and networked synchronization.
For engineers reviewing the R5F572NNDGBG#20 datasheet, R5F572NNDGBG#20 pinout, R5F572NNDGBG#20 application, or R5F572NNDGBG#20 equivalent, key selection criteria include IEEE 1588 timestamping accuracy, dual CAN FD channel isolation, flash ECC coverage, SRAM parity configuration, and Ethernet PHY interface compatibility (MII/RMII).
Technical Context
The R5F572NNDGBG#20 implements the RXv3 CPU core with FPU and double-precision floating-point coprocessor, supporting VFPv3-D16 instruction set. Its system architecture integrates a 32-bit AXI bus matrix, multi-layer AHB/APB bridges, and dedicated DMA channels for Ethernet, USB, and SPI peripherals.
Real-time performance is enhanced by the on-chip timer unit (MTU3) with 32-bit counter resolution, 16-bit PWM timers (TPU), and a 24-channel event link controller (ELC) enabling zero-cycle peripheral triggering without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit superscalar core with FPU and double-precision coprocessor, enabling deterministic floating-point math for servo algorithms. |
| Max Clock Frequency | 240 MHz - delivers 416.7 DMIPS @ 2.7–3.6 V supply, sufficient for multi-axis motion control loop execution within 50 µs. |
| Flash Memory | 4 MB with ECC, sector erase, and background operation - supports safe firmware updates via dual-bank swapping. |
| SRAM | 1 MB with configurable parity/ECC - allows critical control variables and stack data to be protected against single-bit errors. |
| Ethernet Interface | IEEE 802.3 10/100 Mbps MAC with full IEEE 1588-2008 hardware timestamping (nanosecond resolution) - enables precise time-synchronized distributed I/O. |
| CAN FD Support | Dual independent CAN FD controllers (ISO 11898-1:2015), each supporting up to 8 Mbps data phase - suitable for high-bandwidth drive commissioning and diagnostics. |
| Security Features | Hardware AES-128/256, SHA-1/224/256, TRNG, and secure boot ROM - meets IEC 62443-3-3 SL2 requirements for industrial firmware integrity. |
Pinout & Package
This device is packaged in a 176-pin LFBGA (12 mm × 12 mm, 0.8 mm pitch) with exposed thermal pad. Pin functions are defined per R01DS0343EJ Datasheet Rev.1.20 Section 1.5.2 and Section 1.6.2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P1_00 / ETXD0 | Ethernet Transmit Data 0 | Drives bit 0 of MII-mode Ethernet transmit data bus; requires 50 Ω series termination to minimize signal reflection. |
| P1_01 / ETXD1 | Ethernet Transmit Data 1 | Drives bit 1 of MII-mode Ethernet transmit data bus; must be routed with matched length to ETXD0–ETXD3 and ETXEN. |
| P1_04 / ETXEN | Ethernet Transmit Enable | Active-high strobe synchronizing Ethernet transmit data; timing-critical path requiring <1 ns skew vs. ETXD signals. |
| P1_08 / ERXDV | Ethernet Receive Data Valid | Indicates valid receive data on ERXD[3:0]; used by MAC to latch incoming frames - must meet setup/hold relative to ERXCK. |
| P1_12 / ERXCK | Ethernet Receive Clock | 25 MHz input clock for MII receive path; sourced externally or from PHY; jitter <50 ps RMS ensures reliable frame capture. |
| P2_00 / CAN0TX | CAN FD Channel 0 Transmit | High-speed differential driver output (dominant/recessive) - connects directly to CAN transceiver TXD pin. |
| P2_01 / CAN0RX | CAN FD Channel 0 Receive | High-impedance CMOS input sampling CANH/CANL differential state - requires external transceiver RXD connection. |
| P2_04 / CAN1TX | CAN FD Channel 1 Transmit | Independent physical layer output for redundant or multi-network topology - electrically isolated from CAN0 channel. |
| P2_05 / CAN1RX | CAN FD Channel 1 Receive | Separate input for second CAN FD bus - enables concurrent communication on two isolated networks (e.g., control + safety). |
| VDDA | Analog Power Supply | 3.3 V ±5 % dedicated supply for ADC, DAC, and analog comparators - requires local 10 µF + 100 nF decoupling. |
| VSSA | Analog Ground | Isolated ground plane for analog circuits - must be connected to digital ground at single point near power entry. |
| RESET | Active-Low Reset Input | Asynchronous reset assertion halts CPU, clears registers, and forces boot vector fetch - requires 100 ns minimum pulse width. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Hardware Timestamping | Sub-nanosecond resolution timestamp generation on Ethernet Rx/Tx events - eliminates software interrupt latency for time-critical synchronization. |
| Dual Independent CAN FD Controllers | Each supports programmable bit rates up to 8 Mbps data phase and 1 Mbps arbitration - enables simultaneous motion control and safety diagnostics on separate buses. |
| Hardware Encryption Engine | Dedicated AES-128/256, SHA-224/256, and TRNG blocks operating independently of CPU - reduces firmware signing latency to <10 µs per 256-byte block. |
| Event Link Controller (ELC) | 24-channel programmable trigger router - allows peripherals (e.g., ADC, TPU, MTU3) to initiate actions without CPU wake-up or ISR overhead. |
| Flash Memory with Background Operation | Supports read-while-write (RWW) and sector erase during program execution - enables seamless over-the-air firmware updates without stopping real-time tasks. |
Applications
| Industrial PLC Controller | Motion Control Drive |
|---|---|
Use Scenario: Central logic unit in modular PLC rack handling I/O scanning, ladder logic execution, and EtherCAT master coordination. IC Role / Device Role / Timing Role: Main application processor executing real-time OS (e.g., RTOS or bare-metal scheduler), managing Ethernet/IP and Modbus TCP stacks, and servicing fieldbus interrupts. Use Value: Integrated IEEE 1588 timestamping enables sub-microsecond synchronization across distributed I/O modules, meeting IEC 61131-3 cycle time requirements ≤1 ms. | Use Scenario: Embedded controller in servo drive managing position loop, current loop, and field-oriented control (FOC) calculations. IC Role / Device Role / Timing Role: Real-time computation engine running FOC algorithm at 20 kHz, interfacing with external gate drivers and current sensors via high-speed ADC and PWM outputs. Use Value: Dual CAN FD interfaces allow simultaneous commissioning (CANopen) and functional safety monitoring (CAN Safety), while hardware FPU accelerates trigonometric and matrix operations in <2 µs. |
| Factory Automation Gateway | Smart Power Inverter |
Use Scenario: Protocol translator bridging legacy RS-485 field devices (Modbus RTU) to cloud-connected Ethernet backbone (MQTT over TLS). IC Role / Device Role / Timing Role: Secure edge node performing protocol conversion, TLS 1.2 handshake acceleration, and encrypted data buffering before transmission. Use Value: On-chip AES-256 and SHA-256 engines reduce TLS handshake time by 65% versus software-only implementation, enabling 100+ concurrent device connections. | Use Scenario: Grid-tied solar inverter controller managing MPPT, DC-AC conversion, anti-islanding detection, and grid compliance (IEEE 1547). IC Role / Device Role / Timing Role: Safety-certified control MCU coordinating high-frequency PWM generation, isolation monitoring, and fault logging with time-stamped event records. Use Value: Flash ECC and SRAM parity detect and correct single-bit errors in safety-critical variables, satisfying IEC 61508 SIL2 diagnostic coverage requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MNDGBG#20 | Same RX72N Group, identical package and pinout, but with 2 MB flash and 512 KB SRAM - no IEEE 1588 hardware timestamping. | Suitable for cost-sensitive motion controllers where nanosecond-level Ethernet synchronization is not required. | Select when application does not require IEEE 1588 or full 4 MB flash; lower BOM cost with same footprint. |
| R5F566TKDDFK#30 | RX66T Group part: 160 MHz max, 1 MB flash, no Ethernet MAC, dual CAN FD, enhanced motor control timers (MTU3 + DTCP). | Optimized for high-speed motor control (e.g., spindle drives) with advanced PWM dead-time and phase-shift control - lacks networking capability. | Choose for standalone motor control without Ethernet connectivity; superior PWM resolution and phase control versus R5F572NNDGBG#20. |
Compared with R5F572MNDGBG#20, the R5F572NNDGBG#20 adds IEEE 1588 timestamping and doubles flash/SRAM capacity - essential for complex protocol stacks and firmware resilience. Versus R5F566TKDDFK#30, it trades motor-specific peripherals for industrial networking features, making it better suited for distributed control nodes rather than embedded drive cores.
Availability
R5F572NNDGBG#20 is available at Aetrix Electronics and suitable for industrial PLCs, motion control drives, factory automation gateways, and smart power inverters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for R5F572NNDGBG#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and infrastructure markets.
The RX72N Group, including R5F572NNDGBG#20, was designed for real-time industrial automation applications demanding integrated Ethernet, deterministic motion control, and functional safety support - targeting IEC 61508 and UL 61800-5-1 compliance.
FAQ
What is the maximum operating frequency of the R5F572NNDGBG#20?
The R5F572NNDGBG#20 operates at a maximum CPU frequency of 240 MHz under specified voltage (2.7–3.6 V) and temperature (–40°C to +105°C) conditions. This frequency is achieved using the on-chip PLL with external crystal input (typically 12 MHz or 20 MHz), and all peripheral clocks are derived from this source with programmable dividers. The R5F572NNDGBG#20 maintains full functionality-including Ethernet MAC, CAN FD, and USB-at this speed, as verified in Renesas' R01DS0343EJ Datasheet Rev.1.20 Section 23.2.
Does the R5F572NNDGBG#20 include hardware support for IEEE 1588 Precision Time Protocol?
Yes, the R5F572NNDGBG#20 integrates full IEEE 1588-2008 hardware timestamping in its Ethernet MAC, capable of capturing transmit and receive timestamps with nanosecond resolution. It supports one-step and two-step clock correction modes, PTP event message filtering, and hardware-assisted delay measurement (peer-to-peer or end-to-end). This feature is documented in Section 34.4.2 of the RX72N Group User's Manual: Hardware (Rev.1.20), and is active only when the Ethernet MAC is enabled and configured in MII/RMII mode.
What security features are implemented in hardware on the R5F572NNDGBG#20?
The R5F572NNDGBG#20 includes dedicated hardware accelerators for AES-128/256 (ECB/CBC/CTR modes), SHA-1/224/256, and a true random number generator (TRNG) compliant with NIST SP800-90B. It also supports secure boot from internal flash with signature verification (RSA-2048), memory protection unit (MPU) with 16 regions, and tamper-detection pins. These features are detailed in Sections 28.1–28.5 of the R01DS0343EJ Datasheet and enable compliance with IEC 62443-3-3 SL2 for industrial firmware integrity.
How many CAN FD interfaces does the R5F572NNDGBG#20 support, and what are their key capabilities?
The R5F572NNDGBG#20 integrates two independent CAN FD controllers compliant with ISO 11898-1:2015. Each supports programmable bit rates up to 8 Mbps in the data phase and 1 Mbps in arbitration, flexible data length (up to 64 bytes), and built-in error counters and FIFO buffers. They operate concurrently with no shared resources, allowing separate network domains (e.g., control bus and safety bus). Pin assignments are fixed per package: CAN0 uses P2_00/P2_01 and CAN1 uses P2_04/P2_05, as confirmed in Section 1.6.2 of the User's Manual.
What is the flash memory configuration of the R5F572NNDGBG#20, and does it support background operation?
The R5F572NNDGBG#20 contains 4 MB of on-chip flash memory with built-in ECC (single-bit correction, double-bit detection), sector erase capability, and full background operation support - meaning code execution continues uninterrupted during erase or write operations. It supports dual-bank swap for safe firmware updates and includes a secure boot ROM that verifies signed images prior to execution. These specifications are validated in Section 22.1 of the R01DS0343EJ Datasheet Rev.1.20 and apply exclusively to the R5F572NNDGBG#20 variant.
R5F572NNDGBG#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RX
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 136
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NNDGBG#20 FAQ
1.How can I place an order for R5F572NNDGBG#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NNDGBG#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NNDGBG#20 reliable?
The price and inventory of R5F572NNDGBG#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NNDGBG#20 is usually 5 days.
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Once your R5F572NNDGBG#20 order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for R5F572NNDGBG#20?
For technical support, including R5F572NNDGBG#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NNDGBG#20 requirements.
6.How does Aetrix verify that R5F572NNDGBG#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NNDGBG#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NNDGBG#20 meets industry standards.
7.What is the process for return or replacement of R5F572NNDGBG#20?
All R5F572NNDGBG#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NNDGBG#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NNDGBG#20 part is unused and in its original packaging.
Return procedure for R5F572NNDGBG#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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