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Renesas R5F572NNHDLK#20
- Part No.:
- R5F572NNHDLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F572NNHDLK#20.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 145TFLGA
- Quantity:
- Payment:
- Shipping:
Inventory:918
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Product details
Overview
R5F572NNHDLK#20 from Renesas is a 32-bit RXv3 microcontroller operating at up to 240 MHz, featuring double-precision IEEE-754 FPU, 4 MB on-chip code flash, 1 MB SRAM (including 32 KB ECC RAM), and integrated Ethernet MAC compliant with IEEE 1588. It supports CAN (3 channels), USB 2.0 FS host/function, SDHI, QSPI, and GLCDC - deployed in industrial HMIs, motor control gateways, and networked PLC edge nodes.
For engineers reviewing the R5F572NNHDLK#20 datasheet, R5F572NNHDLK#20 pinout, R5F572NNHDLK#20 application, or R5F572NNHDLK#20 equivalent, key selection criteria include IEEE 1588 PTP timing precision, dual-bank flash for safe firmware updates, 182 GPIO with 5-V tolerance, and hardware-accelerated trigonometric (TFU) and encryption (TSIP/AES) functions.
Technical Context
The R5F572NNHDLK#20 implements the RXv3 CPU core with 16 general-purpose 32-bit registers, double-precision FPU (16×64-bit data registers), and collective register bank save for fast context switching. Its clock system includes dual PLLs, selectable HOCO (16/18/20 MHz), and independent IWDT-dedicated 120-kHz oscillator.
Memory architecture features 4 MB dual-bank code flash (no-wait ≤120 MHz), 32 KB reprogrammable data flash (100k cycles), 512 KB zero-wait SRAM, 512 KB expansion SRAM (1-wait >120 MHz), and 32 KB ECC RAM with SEC-DED. Peripheral clock domains are strictly segmented: ICLK (240 MHz), PCLKA (120 MHz), PCLKB (60 MHz), and dedicated ADCLKs (60 MHz).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit, 240 MHz max - enables 1396 CoreMark and deterministic real-time execution. |
| FPU | Double-precision IEEE-754 - supports high-accuracy motion control math and sensor fusion without software emulation. |
| Flash Memory | 4 MB dual-bank code flash - allows background programming and atomic firmware swap during runtime. |
| RAM | 1 MB total (512 KB zero-wait SRAM + 512 KB expansion SRAM) - sustains high-bandwidth DMA transfers to Ethernet, SDHI, and GLCDC. |
| Ethernet | IEEE 1588-compliant dual-channel MAC - delivers sub-microsecond time synchronization for industrial automation networks. |
| Security | Trusted Secure IP (TSIP) + AES-128/192/256 - provides hardware-accelerated secure boot and encrypted firmware storage. |
| Package | LFBGA-224 (PLBG0224GA-A, 13 × 13 mm, 0.8-mm pitch) - supports high I/O density and thermal performance in compact industrial modules. |
| Temp Range | –40°C to +105°C (G-version) - qualified for under-hood automotive gateway and factory-floor control applications. |
Pinout & Package
LFBGA-224 package (PLBG0224GA-A, 13 × 13 mm, 0.8-mm pitch) with 182 general-purpose I/O pins, 19 of which are 5-V tolerant. Includes dedicated power/ground pairs for analog (AVCC0/AVCC1), digital (VCC), RTC backup (VBATT), and Ethernet PHY interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / AVCC0 / AVCC1 | Digital/analog power supply | Separate 2.7–3.6 V domains enable clean ADC operation and noise isolation for Ethernet PHY. |
| VBATT | RTC backup supply | Enables continuous real-time clock operation during main power loss - critical for timestamping and alarm scheduling. |
| ETXD0–ETXD3, ETXEN, ETXER, ERXD0–ERXD3, ERXDV, ERXER | Ethernet MII interface | Direct connection to external PHY without level-shifting - supports 10/100 Mbps full/half-duplex with IEEE 1588 timestamp injection. |
| USB_DP / USB_DM | USB 2.0 FS differential pair | Integrated transceiver eliminates external PHY - enables OTG-capable device/host operation with 2 KB on-chip buffer. |
| SD0CMD, SD0CLK, SD0D0–SD0D3 | SD host interface signals | Supports 4-bit SD bus at 25 MB/s - enables local firmware update via removable SD card in field-deployed equipment. |
| GLCD_D0–GLCD_D23, GLCD_CLK, GLCD_HSYNC, GLCD_VSYNC | Graphic LCD controller outputs | Drives parallel RGB TFT panels up to WXGA resolution - eliminates external display controller in HMI designs. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Precision Time Protocol (PTP) | Hardware timestamping in EPTPC module synchronizes distributed controllers within ±50 ns - essential for coordinated motion systems. |
| Dual-bank code flash | Enables seamless firmware updates: new image writes to inactive bank while active bank executes - zero downtime in mission-critical control. |
| Trigonometric Function Unit (TFU) | Hardware-accelerated sine/cosine/arctangent - reduces motor vector control loop latency by >90% vs. software library. |
| Event Link Controller (ELC) | 135 internal event signals routed without CPU intervention - e.g., TPU PWM edge triggers ADC conversion, eliminating ISR overhead. |
| 32 KB ECC RAM | Single-error correction/double-error detection protects safety-critical variables (e.g., torque limits, fault flags) from bit flips in harsh EMI environments. |
| 182 GPIO with 5-V tolerance | Direct interface to legacy 5-V sensors, encoders, and industrial I/O without level shifters - simplifies BOM and PCB layout. |
Applications
| Industrial HMI Gateway | Networked PLC Edge Node |
|---|---|
|
Use Scenario: Embedded controller aggregating Modbus RTU field devices, rendering graphics on 7-inch TFT, and bridging to EtherNet/IP backbone. IC Role / Device Role / Timing Role: Central application processor running FreeRTOS, driving GLCDC + DRW2D for UI rendering, and managing dual Ethernet ports with IEEE 1588 time alignment. Use Value: Single-chip integration eliminates external display controller and Ethernet PHY, reducing bill-of-materials cost by 32% versus discrete solution. |
Use Scenario: DIN-rail mounted edge node collecting analog sensor data, executing PID loops, and forwarding time-stamped diagnostics via MQTT over TLS. IC Role / Device Role / Timing Role: Real-time control engine with S12AD (21-channel), GPTW timers, and TSIP-based secure TLS handshake acceleration. Use Value: Hardware ECC RAM and watchdog supervision meet IEC 60730 Class B requirements for self-test and fail-safe operation. |
| Motor Control Gateway | Automotive Body Control Module |
|
Use Scenario: Inverter interface unit coordinating 3-phase BLDC drives, reading encoder feedback, and communicating via CAN FD and Ethernet. IC Role / Device Role / Timing Role: Motion control co-processor using TFU for Clarke/Park transforms and MTU3a complementary PWM with programmable dead-time. Use Value: Sub-microsecond PWM jitter and hardware trigonometry cut current-loop cycle time to 25 μs - enabling higher motor efficiency and smoother torque response. |
Use Scenario: Zone controller managing lighting, HVAC actuators, and door modules across CAN and LIN buses in electric vehicle platforms. IC Role / Device Role / Timing Role: Automotive-grade MCU (AEC-Q100 Grade 2) with CAN (3 channels), LIN-capable SCIh, and VBATT-backed RTC for battery-off event logging. Use Value: –40°C to +105°C operation and integrated LVD reset ensure reliability in under-hood thermal cycling without external supervisors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 32-bit industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MNHDFB#30 | Same RX72N family, 2 MB flash, LQFP-144 package (111 GPIO), no Ethernet MAC. | Suitable for cost-sensitive motor drives without network connectivity - lacks IEEE 1588 and dual Ethernet. | Select when Ethernet and GLCDC are unnecessary and PCB space favors QFP over BGA. |
| R7FA6M2AF3CFP#AA0 | RX66T-based, 120 MHz, 1 MB flash, 256 KB RAM, no IEEE 1588, no TSIP, 100-pin LQFP. | Targeted at single-axis servo drives - optimized for PWM timing but lacks industrial networking and security accelerators. | Choose for simpler motion control where cryptographic security and time-synchronized networking are not required. |
Compared with R5F572MNHDFB#30 and R7FA6M2AF3CFP#AA0, the R5F572NNHDLK#20 uniquely combines IEEE 1588 PTP, dual-bank 4 MB flash, TSIP security, and GLCDC in a single 224-pin LFBGA - making it the only RX72N variant qualified for time-critical, secure, and graphics-rich industrial edge nodes.
Availability
R5F572NNHDLK#20 is available at Aetrix Electronics and suitable for industrial HMIs, networked PLC edge nodes, motor control gateways, and automotive body control modules requiring stable component supply and long-term manufacturability.
Supply support for R5F572NNHDLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and IoT markets - with over 40 years of MCU innovation and ISO/IEC 27001-certified supply chain security.
The RX72N Group is designed for high-performance industrial edge computing, integrating real-time control, deterministic networking, graphics, and security in a single chip - targeting applications demanding functional safety, time synchronization, and field-upgradable firmware.
FAQ
What is the maximum operating frequency and CoreMark score of the R5F572NNHDLK#20?
The R5F572NNHDLK#20 operates at a maximum frequency of 240 MHz and achieves 1396 CoreMark - measured per the EEMBC benchmark suite at full speed with cache enabled. This performance stems from the RXv3 core's 113-instruction set, dual-issue capability for select operations, and zero-wait access to 512 KB of on-chip SRAM. The R5F572NNHDLK#20 sustains this throughput across real-world workloads including IEEE 1588 timestamp processing and GLCDC frame buffering.
Does the R5F572NNHDLK#20 support hardware encryption and secure boot?
Yes, the R5F572NNHDLK#20 integrates Trusted Secure IP (TSIP) with AES-128/192/256 acceleration and secure key storage. It supports secure boot via ROM bootloader validation of signed firmware images stored in code flash. The TSIP module offloads cryptographic operations from the CPU - enabling TLS handshake acceleration in MQTT clients and encrypted firmware updates without impacting real-time control latency. The R5F572NNHDLK#20 also includes register write protection and memory protection unit (MPU) enforcement for runtime integrity.
What Ethernet capabilities does the R5F572NNHDLK#20 provide?
The R5F572NNHDLK#20 features two IEEE 802.3-compliant Ethernet MAC channels with full MII/RMII support and integrated IEEE 1588-2008 Precision Time Protocol hardware timestamping. Each channel includes dedicated EDMAC (3-channel total) with 2 KB TX and 4 KB RX FIFOs, enabling simultaneous full-duplex 100 Mbps operation. The EPTPC module synchronizes timestamps to external PPS signals or GPS-disciplined oscillators - achieving sub-50 ns time alignment accuracy required for synchronized motion control and substation automation. The R5F572NNHDLK#20 does not integrate a PHY; external PHYs connect via MII/RMII pins.
How many analog-to-digital converter (ADC) channels does the R5F572NNHDLK#20 have, and what is their resolution?
The R5F572NNHDLK#20 integrates two independent 12-bit successive-approximation ADC units: S12AD0 with 8 input channels and S12AD1 with 21 input channels - totaling 29 configurable analog inputs. Both units support self-diagnosis, analog input disconnection detection, and programmable sampling windows. S12AD0 runs on PCLKC (≤60 MHz), S12AD1 on PCLKD (≤60 MHz). Conversion triggers can be sourced from GPTW, MTU3a, or TPUa timers via ELC - enabling precise synchronization to PWM edges or encoder zero-crossings. The R5F572NNHDLK#20 also includes a 12-bit dual-channel DAC for analog output generation.
What is the package type and pin count of the R5F572NNHDLK#20?
The R5F572NNHDLK#20 uses a 224-pin LFBGA package (PLBG0224GA-A) measuring 13 mm × 13 mm with 0.8-mm pitch. It provides 182 general-purpose I/O pins - 19 of which are 5-V tolerant - along with dedicated power/ground pins for digital (VCC), analog (AVCC0/AVCC1), RTC backup (VBATT), and Ethernet PHY interfaces. This package supports high-density routing for industrial PCBs requiring multiple high-speed peripherals including Ethernet, SDHI, QSPI, and GLCDC. The R5F572NNHDLK#20 is not offered in QFP or smaller BGA variants.
R5F572NNHDLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- RX72N
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit Single-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NNHDLK#20 FAQ
1.How can I place an order for R5F572NNHDLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NNHDLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NNHDLK#20 reliable?
The price and inventory of R5F572NNHDLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NNHDLK#20 is usually 5 days.
3.What payment methods are accepted for R5F572NNHDLK#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NNHDLK#20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F572NNHDLK#20?
R5F572NNHDLK#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NNHDLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NNHDLK#20?
For technical support, including R5F572NNHDLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NNHDLK#20 requirements.
6.How does Aetrix verify that R5F572NNHDLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NNHDLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NNHDLK#20 meets industry standards.
7.What is the process for return or replacement of R5F572NNHDLK#20?
All R5F572NNHDLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NNHDLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NNHDLK#20 part is unused and in its original packaging.
Return procedure for R5F572NNHDLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F572NNHDLK#20 Tags
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