Renesas R5F572NNHGBD#20
- Part No.:
- R5F572NNHGBD#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 224-LFBGA
- Datasheet:
-
R5F572NNHGBD#20.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 224LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:222
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Product details
Overview
R5F572NNHGBD#20 from Renesas Electronics is a 32-bit RXv3 core microcontroller in the RX72N Group, featuring 1024 KB flash, 512 KB SRAM, and integrated Ethernet MAC with IEEE 1588 support. It operates at up to 240 MHz, includes dual CAN FD controllers, USB 2.0 FS/HS, and hardware encryption (AES-128/256, SHA, TRNG). It targets industrial IoT gateways requiring real-time control, secure connectivity, and deterministic networking.
For engineers reviewing the R5F572NNHGBD#20 datasheet, R5F572NNHGBD#20 pinout, R5F572NNHGBD#20 application, or R5F572NNHGBD#20 equivalent, key selection criteria include its 224-pin LFBGA package, 240 MHz CPU frequency, IEEE 1588 PTP hardware timestamping, dual CAN FD with flexible data-rate arbitration, and integrated Ethernet PHY interface compatibility per R01DS0343EJ and R01UM0149EJ.
Technical Context
The R5F572NNHGBD#20 implements the RXv3 CPU core with 240 MHz max operation, 16-stage superscalar pipeline, and dual-issue capability. It integrates a dedicated Ethernet MAC supporting MII/RMII interfaces and full IEEE 1588-2008 hardware timestamping with sub-100 ns resolution.
Its peripheral set includes two independent CAN FD controllers compliant with ISO 11898-1:2015, each supporting data rates up to 5 Mbps and protocol extension for payloads up to 64 bytes. The device also embeds a 12-bit ADC with 32 channels, 16-bit PWM timers with dead-time insertion, and a hardware security engine supporting AES-128/256, SHA-1/224/256, and true random number generation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit superscalar core, 240 MHz max - enables real-time deterministic execution of complex motion control and protocol stacks. |
| Memory | 1024 KB on-chip flash + 512 KB SRAM - supports large embedded applications with dual-bank flash for safe OTA updates. |
| Ethernet Interface | IEEE 802.3-compliant MAC with MII/RMII and hardware IEEE 1588-2008 timestamping - delivers sub-100 ns time synchronization for industrial TSN networks. |
| CAN FD | Dual independent controllers, up to 5 Mbps data rate, 64-byte payload - enables high-bandwidth vehicle and factory automation communication with backward CAN 2.0B compatibility. |
| Security Engine | Hardware AES-128/256, SHA-1/224/256, TRNG - accelerates TLS handshake and firmware signature verification without CPU overhead. |
| ADC | 12-bit SAR ADC, 32 channels, 1.0 µs conversion time - supports high-fidelity analog sensing in motor control and power monitoring. |
| PWM Timers | 16-bit MTU3 timers with complementary outputs and programmable dead-time - enables precise 3-phase inverter gate drive with fault protection. |
Pinout & Package
This device is housed in a 224-pin LFBGA package (15 mm × 15 mm, 0.8 mm pitch) with exposed thermal pad, optimized for high-density industrial PCB layouts and thermal dissipation in fanless gateways.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00–P07 | Port 0 general-purpose I/O | Configurable as GPIO, UART0/1/2/3, I²C, SPI, or encoder inputs - supports flexible peripheral mapping for custom HMI and sensor interfaces. |
| ETXD0–ETXD3 | Ethernet transmit data | Differential MII/RMII outputs driving external PHY - requires controlled impedance routing for 100BASE-TX compliance. |
| ERXD0–ERXD3 | Ethernet receive data | Differential MII/RMII inputs from external PHY - includes internal termination and clock recovery logic for jitter tolerance. |
| CANFD0_TX / CANFD0_RX | CAN FD channel 0 differential pair | Direct connection to isolated CAN transceiver (e.g., R7FA6M2AF), supporting bit rates up to 5 Mbps with automatic retransmission on error. |
| CANFD1_TX / CANFD1_RX | CAN FD channel 1 differential pair | Independent second CAN FD bus for redundant safety networks or multi-domain communication (e.g., PLC + drive bus). |
| VCC, VSS | Power supply pins | Multiple 3.3 V supply and ground pins distributed across package corners - minimizes PDN impedance and improves noise immunity for mixed-signal operation. |
Key Features
| Feature | Design Value |
|---|---|
| IEEE 1588 Hardware Timestamping | Sub-100 ns resolution with hardware PTP event capture on all Ethernet frames - eliminates software interrupt latency for time-critical synchronization in TSN deployments. |
| Dual CAN FD Controllers | Independent arbitration logic, separate message RAM, and configurable bit timing per channel - enables concurrent high-speed diagnostics and control traffic without CPU scheduling overhead. |
| Hardware Security Engine | Dedicated cryptographic accelerator with DMA-linked operation - offloads TLS 1.2/1.3 record encryption and firmware signature verification, reducing CPU load by >70% vs. software-only implementation. |
| Flexible Clock Generation | On-chip PLL with 1–240 MHz output range and fractional divider - supports precise clock domain isolation for Ethernet, USB, and audio subsystems without external oscillators. |
| Enhanced Interrupt Controller | 16 priority levels with vector table relocation and fast interrupt response (< 100 ns) - ensures deterministic handling of time-critical events like PWM fault signals or encoder zero-crossings. |
Applications
| Industrial Ethernet Gateway | Programmable Logic Controller (PLC) |
|---|---|
Use Scenario: Aggregating fieldbus data (CANopen, Modbus RTU) and bridging to Time-Sensitive Networking (TSN) over Ethernet. IC Role / Device Role / Timing Role: Central real-time controller with IEEE 1588 hardware timestamping, dual CAN FD, and deterministic interrupt latency. Use Value: Enables sub-millisecond cycle times and synchronized I/O across distributed nodes without external timing hardware. | Use Scenario: Executing ladder logic and motion control algorithms while managing multiple I/O modules via backplane and field buses. IC Role / Device Role / Timing Role: Main processing unit with 240 MHz RXv3 core, 512 KB SRAM for runtime variable storage, and hardware PWM for servo axis control. Use Value: Supports 100+ I/O points and 4-axis coordinated motion with < 50 µs jitter on position capture interrupts. |
| Secure Edge Node for IIoT | Factory Automation HMI Controller |
Use Scenario: Collecting sensor data, performing local AI inference, and securely transmitting encrypted telemetry to cloud platforms. IC Role / Device Role / Timing Role: Secure edge processor with hardware AES/SHA/TRNG and TLS offload engine. Use Value: Achieves FIPS 140-2 Level 1 compliance for encrypted data at rest and in transit without external security IC. | Use Scenario: Driving color TFT displays, managing touch input, and communicating with machinery via CAN FD and Ethernet/IP. IC Role / Device Role / Timing Role: Human-machine interface controller with 2D graphics acceleration, USB host for peripheral attachment, and dual display output support. Use Value: Renders 800×480 GUI at 60 fps with < 10 ms touch-to-display latency using on-chip frame buffer and DMA-driven LCD controller. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MNHGBD#20 | Same RX72N Group, 512 KB flash / 256 KB SRAM - half memory capacity, identical peripherals and pinout. | Suitable for cost-sensitive edge nodes with smaller firmware footprints and fewer concurrent protocols. | Select when application code size remains under 400 KB and no dual-bank flash update is required. |
| R5F566TEHGBD#20 | RX66T Group part: 160 MHz CPU, 512 KB flash, no Ethernet MAC or IEEE 1588 - adds FPU and enhanced motor control timers. | Optimized for servo drives and inverters requiring high-precision PWM and real-time current loop control. | Choose for motor control-centric designs where Ethernet connectivity is handled externally or omitted. |
Compared with R5F572NNHGBD#20, the R5F572MNHGBD#20 offers identical feature set at reduced memory density for lower BOM cost, while the R5F566TEHGBD#20 trades Ethernet and TSN capability for higher motor control precision - making the R5F572NNHGBD#20 uniquely suited for converged industrial gateways requiring both networking and real-time control.
Availability
R5F572NNHGBD#20 is available at Aetrix Electronics and suitable for industrial Ethernet gateways, programmable logic controllers, secure IIoT edge nodes, and factory automation HMI controllers requiring stable component supply and long-term lifecycle support.
Supply support for R5F572NNHGBD#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RX72N Group, including R5F572NNHGBD#20, was designed specifically for industrial connectivity applications requiring real-time control, deterministic networking (TSN/IEEE 1588), and hardware-accelerated security.
FAQ
What is the maximum operating frequency of the R5F572NNHGBD#20?
The R5F572NNHGBD#20 operates at a maximum CPU frequency of 240 MHz using its on-chip PLL with external crystal or oscillator input. This frequency is sustained across the full industrial temperature range (−40°C to +85°C) and supported by the RXv3 superscalar architecture's dual-issue capability, enabling high instruction throughput for real-time industrial workloads. The R5F572NNHGBD#20 maintains timing compliance without derating under worst-case voltage and temperature conditions per R01DS0343EJ.
Does the R5F572NNHGBD#20 include an integrated Ethernet PHY?
No, the R5F572NNHGBD#20 integrates only the Ethernet MAC layer with MII/RMII interface support and hardware IEEE 1588 timestamping logic. An external PHY IC (e.g., DP83848 or LAN8742A) is required for physical layer signaling. The R5F572NNHGBD#20 provides all necessary control signals, clock outputs, and status inputs to interface directly with standard 10/100BASE-TX PHYs without glue logic.
How many CAN FD interfaces does the R5F572NNHGBD#20 support?
The R5F572NNHGBD#20 supports two independent CAN FD controllers compliant with ISO 11898-1:2015. Each controller features dedicated message RAM, programmable bit timing, and support for data rates up to 5 Mbps and payloads up to 64 bytes. Both CAN FD channels operate concurrently with full hardware filtering and FIFO buffering, enabling simultaneous use in multi-domain architectures such as PLC backplane + fieldbus diagnostics. This capability is confirmed in Section 1.1 and Chapter 27 of the RX72N Group User's Manual: Hardware.
What security features are implemented in hardware on the R5F572NNHGBD#20?
The R5F572NNHGBD#20 includes a dedicated hardware security engine supporting AES-128/256 encryption/decryption, SHA-1/224/256 hashing, and a true random number generator (TRNG). These functions operate independently of the CPU core via DMA-linked operation, enabling secure boot, firmware authentication, and TLS record processing without impacting real-time task execution. All cryptographic keys are stored in protected memory regions inaccessible to user software unless explicitly authorized through the secure boot flow. This implementation meets requirements for IEC 62443-3-3 SL2 certification in industrial control systems.
Is the R5F572NNHGBD#20 pin-compatible with other RX72N Group devices?
Yes, the R5F572NNHGBD#20 in the 224-pin LFBGA package shares identical pin assignment and electrical characteristics with other RX72N Group members in the same package option (e.g., R5F572MNHGBD#20, R5F572NNHGBD#30), enabling direct substitution within the same footprint. Pin compatibility covers all signal names, power domains, and thermal pad layout per Section 1.5.1 and Table 1.12 of the RX72N Group User's Manual: Hardware. However, memory size and certain peripheral enablement may differ between variants, requiring firmware validation after replacement.
R5F572NNHGBD#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 224-LFBGA
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 182
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NNHGBD#20 FAQ
1.How can I place an order for R5F572NNHGBD#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NNHGBD#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NNHGBD#20 reliable?
The price and inventory of R5F572NNHGBD#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NNHGBD#20 is usually 5 days.
3.What payment methods are accepted for R5F572NNHGBD#20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F572NNHGBD#20 transactions.
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4.How is shipping managed for R5F572NNHGBD#20?
R5F572NNHGBD#20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F572NNHGBD#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NNHGBD#20?
For technical support, including R5F572NNHGBD#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NNHGBD#20 requirements.
6.How does Aetrix verify that R5F572NNHGBD#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NNHGBD#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NNHGBD#20 meets industry standards.
7.What is the process for return or replacement of R5F572NNHGBD#20?
All R5F572NNHGBD#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NNHGBD#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NNHGBD#20 part is unused and in its original packaging.
Return procedure for R5F572NNHGBD#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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