Renesas R5F572NNHGLK#20
- Part No.:
- R5F572NNHGLK#20
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 145-TFLGA
- Datasheet:
-
R5F572NNHGLK#20.pdf
- Description:
- IC MCU 32BIT 4MB FLASH 145TFLGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F572NNHGLK#20 from Renesas Electronics is a 32-bit RXv3 core microcontroller in the RX72N Group, featuring 4 MB flash memory, 1 MB SRAM, dual CAN FD interfaces, and integrated Ethernet MAC with IEEE 1588 support. It operates at up to 240 MHz, includes hardware encryption (AES-128/256, SHA, TRNG), and targets industrial PLCs, HMIs, and networked motion controllers requiring real-time deterministic response and secure connectivity.
For engineers reviewing the R5F572NNHGLK#20 datasheet, R5F572NNHGLK#20 pinout, R5F572NNHGLK#20 application, or R5F572NNHGLK#20 equivalent, key selection considerations include its 176-pin LFBGA package, dual CAN FD + Ethernet PHY interface capability, 240 MHz real-time execution, hardware crypto acceleration, and industrial temperature grade (−40°C to +85°C) compliance.
Technical Context
The R5F572NNHGLK#20 implements the RXv3 CPU core with 6-stage superscalar pipeline, supporting both little-endian and big-endian operation via software-controlled endian switching. It integrates a dual-bank flash memory controller with background operation (BGO) and automatic erase/write suspend/resume for robust firmware updates.
Its system architecture includes a multi-layer AXI bus matrix, dedicated DMA channels for peripheral-to-memory transfers (including scatter-gather), and a real-time OS-aware interrupt controller with 256 priority levels and fast interrupt vectoring (≤12 cycles). Peripheral integration includes a 12-bit ADC with 32-channel scan, 3x 16-bit timer units with complementary PWM output, and a programmable gain amplifier (PGA) for sensor signal conditioning.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | RXv3 32-bit superscalar core, 240 MHz max - enables hard real-time control loops with sub-1 µs ISR latency. |
| Flash Memory | 4 MB on-chip flash with ECC and BGO - supports live firmware update without halting application execution. |
| SRAM | 1 MB on-chip SRAM with parity - provides deterministic data access for time-critical buffers and RTOS stacks. |
| Connectivity | Dual CAN FD (up to 8 Mbps) + 10/100 Ethernet MAC with IEEE 1588 v2 - enables synchronized multi-axis motion control over industrial networks. |
| Crypto Engine | Hardware AES-128/256, SHA-1/256, TRNG - accelerates secure boot, OTA authentication, and encrypted communication without CPU overhead. |
| Package | 176-pin LFBGA (12 mm × 12 mm, 0.8 mm pitch) - balances I/O count (144 GPIO), thermal performance, and PCB routing density for compact industrial modules. |
| Operating Temp | −40°C to +85°C - qualified for deployment in uncontrolled industrial enclosures and factory-floor HMIs. |
Pinout & Package
Package: 176-pin Low-Profile Fine-Pitch Ball Grid Array (LFBGA), 12 mm × 12 mm, 0.8 mm ball pitch, RoHS-compliant, moisture sensitivity level (MSL) 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00–P07 | GPIO / UART0 TX/RX / I²C0 SCL/SDA | Multi-function port group supporting high-speed serial comms or general-purpose I/O with configurable pull-up/down and slew rate. |
| P10–P17 | GPIO / CAN0 TX/RX / QSPI CLK/IO0–IO3 | Shared CAN FD physical layer interface and quad-SPI flash interface - enables boot-from-QSPI and CAN-based firmware distribution. |
| P20–P27 | GPIO / Ethernet RMII REF_CLK / RXD0–RXD3 / TXD0–TXD3 | Dedicated RMII interface pins with internal 50 Ω termination - eliminates external resistors for simplified 10/100 Ethernet PHY connection. |
| P30–P37 | GPIO / ADC0 AN0–AN7 / PGA IN+ / IN− | Analog input group with integrated programmable gain amplifier - accepts ±10 V industrial sensor signals directly without external signal conditioning. |
| VCC, VSS | Core & I/O Power Supply / Ground | Separate 1.25 V core and 3.3 V I/O rails with dedicated decoupling pads - ensures stable operation under dynamic load switching in noisy factory environments. |
Key Features
| Feature | Design Value |
|---|---|
| Dual CAN FD with ISO 11898-1:2015 compliance | Enables deterministic, high-bandwidth fieldbus communication (up to 8 Mbps) for distributed I/O and servo drive synchronization. |
| Integrated Ethernet MAC with IEEE 1588 hardware timestamping | Supports precise time-synchronized control across networked devices (±50 ns timestamp resolution) without external PHY assistance. |
| Hardware crypto engine with side-channel resistant implementation | Accelerates TLS handshake and secure firmware verification while mitigating timing-based cryptographic attacks in embedded deployments. |
| Real-time trace with SWO and ETM support | Provides non-intrusive instruction and data trace at full 240 MHz speed - essential for debugging deterministic control algorithms and RTOS scheduling. |
| Programmable gain amplifier (PGA) with 1–32× gain | Directly interfaces with low-level analog sensors (e.g., strain gauges, thermocouples), eliminating external op-amp stages and reducing BOM cost. |
Applications
| Industrial PLC Controller | HMI with Networked Visualization |
|---|---|
Use Scenario: Standalone or modular programmable logic controller executing ladder logic and motion control sequences in manufacturing cells. IC Role / Device Role / Timing Role: Main application processor managing I/O scanning, PID loop execution, CAN FD fieldbus coordination, and Ethernet-based supervisory communication. Use Value: 240 MHz RXv3 core delivers ≤100 µs scan cycle times for 128-point I/O systems; dual CAN FD supports daisy-chained remote I/O modules with guaranteed message latency. | Use Scenario: Touch-enabled operator interface with real-time visualization of machine status, production KPIs, and alarm history over factory LAN. IC Role / Device Role / Timing Role: Application host running embedded Linux or FreeRTOS with GUI framework, driving display via RGB interface and communicating via Ethernet and CAN FD. Use Value: Integrated Ethernet MAC + IEEE 1588 enables synchronized HMI updates across multiple stations; 4 MB flash stores full GUI assets and firmware images locally. |
| Secure Edge Gateway | Networked Motion Controller |
Use Scenario: Protocol translation gateway aggregating Modbus RTU, CANopen, and EtherCAT devices into MQTT/OPC UA cloud endpoints. IC Role / Device Role / Timing Role: Secure edge node performing protocol conversion, TLS-encrypted telemetry upload, and local policy enforcement before cloud transmission. Use Value: Hardware AES/SHA/TRNG enables authenticated, encrypted MQTT publish at line rate (100 Mbps Ethernet); 1 MB SRAM buffers burst telemetry during intermittent cloud connectivity. | Use Scenario: Compact servo drive controller coordinating multi-axis position/velocity/torque loops using distributed clock synchronization. IC Role / Device Role / Timing Role: Real-time motion controller executing trajectory planning, current-loop PWM generation, and synchronized CAN FD feedback acquisition. Use Value: Dual CAN FD interfaces support synchronized encoder feedback and command distribution; hardware PWM timers deliver <100 ns jitter for precise motor phase control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F572MNHGLK#20 | Same RX72N Group, 2 MB flash / 512 KB SRAM - reduced memory capacity, identical peripherals and package. | Suitable for cost-sensitive HMIs or gateways with smaller firmware footprints and fewer concurrent tasks. | Select when application firmware size remains under 1.8 MB and runtime RAM usage stays below 450 KB. |
| R5F566TKHDFB#30 | RX66T Group, 1.25 MB flash / 192 KB SRAM, single CAN FD, no Ethernet MAC - different core (RXv2), lower clock (160 MHz). | Targeted at standalone servo drives or inverters where Ethernet is unnecessary and CAN FD suffices for motor feedback. | Choose for simpler motion control applications lacking networked supervision or cloud connectivity requirements. |
Compared with R5F572MNHGLK#20 and R5F566TKHDFB#30, the R5F572NNHGLK#20 uniquely combines 4 MB flash, dual CAN FD, and integrated Ethernet MAC in a single 176-pin LFBGA - enabling consolidated industrial edge nodes that replace discrete gateway + controller architectures.
Availability
R5F572NNHGLK#20 is available at Aetrix Electronics and suitable for industrial automation, factory HMIs, and secure edge gateways requiring stable component supply, long-term lifecycle assurance, and automotive-grade reliability screening.
Supply support for R5F572NNHGLK#20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and enterprise markets.
The RX72N Group - including the R5F572NNHGLK#20 - was designed specifically for real-time industrial automation applications demanding deterministic performance, functional safety readiness (IEC 61508 SIL2-capable), and secure networked operation.
FAQ
What is the maximum operating frequency of the R5F572NNHGLK#20?
The R5F572NNHGLK#20 operates at a maximum CPU frequency of 240 MHz, achieved via its RXv3 superscalar core with six-stage pipeline and on-chip PLL. This frequency is fully supported across the industrial temperature range (−40°C to +85°C) with appropriate voltage regulation and thermal design. The R5F572NNHGLK#20 maintains deterministic timing behavior at this speed, making it suitable for hard real-time control loops in industrial PLCs and motion controllers.
Does the R5F572NNHGLK#20 include an integrated Ethernet PHY?
No, the R5F572NNHGLK#20 integrates only the Ethernet MAC layer compliant with IEEE 802.3u (10/100 Mbps) and IEEE 1588-2008 v2 precision time protocol. An external PHY IC (e.g., DP83848 or LAN8742A) is required for physical layer signaling. However, the R5F572NNHGLK#20 provides RMII interface pins with internal 50 Ω termination resistors and hardware timestamping logic, minimizing external components and ensuring sub-100 ns time synchronization accuracy when paired with a compatible PHY.
What security features are implemented in hardware on the R5F572NNHGLK#20?
The R5F572NNHGLK#20 includes a dedicated hardware crypto engine supporting AES-128/256 (ECB/CBC/CTR/GCM modes), SHA-1/256, and a true random number generator (TRNG) compliant with NIST SP800-90B. These accelerators operate independently of the CPU, enabling secure boot verification, encrypted firmware updates, and TLS offload without compromising real-time performance. The R5F572NNHGLK#20 also supports memory protection units (MPU) and secure debug lock to prevent unauthorized code extraction or modification.
Is the R5F572NNHGLK#20 pin-compatible with other RX72N Group MCUs?
Yes, the R5F572NNHGLK#20 in the 176-pin LFBGA package shares identical pinout and electrical characteristics with other RX72N Group members in the same package variant (e.g., R5F572MNHGLK#20, R5F572NNHGB#20). This allows direct substitution within the same footprint for memory-scaling or feature-tuning during design iteration. However, pin compatibility does not extend across different packages (e.g., 144-pin QFP or 224-pin BGA), and users must verify peripheral register mapping and clock configuration when migrating between variants.
What development tools are officially supported for the R5F572NNHGLK#20?
Renesas provides full toolchain support for the R5F572NNHGLK#20, including e2 studio IDE with GCC RX compiler, CS+ (formerly High-performance Embedded Workshop), and Renesas Flash Programmer. Hardware debugging is enabled via JTAG/SWD using E2 Lite or E2 emulator probes. Additionally, the R5F572NNHGLK#20 is supported by the RX72N Envision Kit (RTK772200C00001BJ) and the RX72N Cloud Kit, both offering pre-integrated Ethernet, CAN FD, and touch HMI capabilities for rapid prototyping. All tools are validated against the R5F572NNHGLK#20 silicon revision and documented in Renesas' official application notes.
R5F572NNHGLK#20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 145-TFLGA
- Series:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- RXv3
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, USB OTG
- Peripherals:
- DMA, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 111
- Program Memory Size:
- 4MB (4M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F572NNHGLK#20 FAQ
1.How can I place an order for R5F572NNHGLK#20 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F572NNHGLK#20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F572NNHGLK#20 reliable?
The price and inventory of R5F572NNHGLK#20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F572NNHGLK#20 is usually 5 days.
3.What payment methods are accepted for R5F572NNHGLK#20?
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Once your R5F572NNHGLK#20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F572NNHGLK#20?
For technical support, including R5F572NNHGLK#20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F572NNHGLK#20 requirements.
6.How does Aetrix verify that R5F572NNHGLK#20 is sourced from the original manufacturer or authorized distributors?
All R5F572NNHGLK#20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F572NNHGLK#20 meets industry standards.
7.What is the process for return or replacement of R5F572NNHGLK#20?
All R5F572NNHGLK#20 units undergo pre-shipment inspection (PSI). If there is an issue with R5F572NNHGLK#20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F572NNHGLK#20 part is unused and in its original packaging.
Return procedure for R5F572NNHGLK#20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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