Renesas R7FA6M5AG2CBG#BC0
- Part No.:
- R7FA6M5AG2CBG#BC0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 176-LFBGA
- Datasheet:
-
R7FA6M5AG2CBG#BC0.pdf
- Description:
- MCU RA6 ARM CM33 200MHZ 1.5M/512
- Quantity:
- Payment:

- Shipping:

Inventory:3,039
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R7FA6M5AG2CBG from Renesas is a high-performance 32-bit Arm Cortex-M33 microcontroller operating at up to 200 MHz, featuring 1.5 MB dual-bank code flash, 8 KB data flash, 512 KB SRAM with parity/ECC, integrated Ethernet MAC, USB 2.0 High-Speed/Full-Speed, dual CAN FD, QSPI/OSPI, and Secure Crypto Engine (SCE9) with TrustZone support - deployed in industrial gateways requiring secure, real-time connectivity and deterministic control.
For engineers reviewing the R7FA6M5AG2CBG datasheet, R7FA6M5AG2CBG pinout, R7FA6M5AG2CBG application, or R7FA6M5AG2CBG equivalent, key selection criteria include its -40°C to +85°C temperature grade, 176-pin FBGA package (PLBG0176GF-A), 200 MHz core clock, dual CAN FD interfaces, and hardware-accelerated AES/RSA/ECC cryptography for secure boot and firmware updates.
Technical Context
The R7FA6M5AG2CBG implements Armv8-M architecture with TrustZone-enforced secure/non-secure execution environments, supporting dual-bank flash SWAP operations for zero-downtime firmware updates. Its memory subsystem includes 512 KB SRAM with configurable parity or ECC protection and 8 KB data flash rated for 100,000 P/E cycles.
Connectivity integrates Ethernet MAC (RMII only), USBHS/USBFS with internal transceivers, two CAN FD controllers (16 TX/RX buffers each), QSPI/OSPI for external memory expansion, and ten SCI channels supporting UART, SPI, I²C, smart card, and Manchester modes - all managed via Event Link Controller (ELC) for CPU-free peripheral coordination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | Arm Cortex-M33 @ 200 MHz max; supports TrustZone security extension and PMSAv8 MPU with 8 secure + 8 non-secure regions. |
| Memory | 1.5 MB dual-bank code flash (SWAP/background operation), 8 KB data flash, 512 KB SRAM with parity/ECC. |
| Operating Temp | -40°C to +85°C; qualified for industrial ambient conditions without derating. |
| Package | 176-pin FBGA (PLBG0176GF-A), 13 × 13 mm, 0.8 mm pitch, Pb-free Sn terminal finish. |
| Peripherals | Dual CAN FD (ISO 11898-1), Ethernet MAC (RMII), USB 2.0 HS/FS, QSPI/OSPI, 10× SCI, 3× I²C, 2× SPI, SDHI, SSIE, CEC. |
| Security | Secure Crypto Engine 9 (AES-128/256, RSA-2048/4096, ECC-256/384, SHA-224/256), tamper detection, lifecycle management. |
| Analog | Two 12-bit ADCs (ADC12) with up to 26 total input channels, two 12-bit DACs (DAC12), on-die temperature sensor (TSN). |
Pinout & Package
176-pin Fine-Pitch Ball Grid Array (FBGA) package, PLBG0176GF-A footprint (13 mm × 13 mm, 0.8 mm pitch), RoHS-compliant Sn terminal plating. Pin functions validated per Renesas R01DS0366EJ0150 Rev.1.50 datasheet Section 1.5.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Primary 2.7–3.6 V core power domain; decoupling required per pin with 0.1 µF ceramic capacitor placed adjacent. |
| VBATT | Battery backup supply | Supplies RTC, SOSC, and backup registers during main power loss; enables calendar retention and wake-from-standby. |
| XTAL / EXTAL | Main crystal oscillator interface | Supports 8–24 MHz external crystal; enables precise timing for USB, Ethernet, and real-time applications. |
| MD / RES | Mode select / Reset input | Hardwired MD pin sets single-chip vs. boot mode; RES is active-low asynchronous reset with internal pull-up. |
| ETH_MDC / ETH_MDIO | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC bus for PHY register configuration and status monitoring. |
| USB_VBUS / USB_DP / USB_DM | USB 2.0 High-Speed interface | Dedicated pins for USBHS device/host operation; internal transceiver eliminates need for external PHY. |
| CANFD0_TX / CANFD0_RX | CAN FD Channel 0 differential pair | Direct connection to CAN FD transceiver; supports bit rates up to 5 Mbps and payload lengths up to 64 bytes. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash SWAP | Enables atomic firmware updates with zero downtime: background programming of inactive bank while executing from active bank. |
| TrustZone + SCE9 | Hardware-isolated secure world with cryptographic accelerators (AES/RSA/ECC/SHA), key vault, and tamper-resistant boot flow. |
| Event Link Controller (ELC) | Configurable hardware routing of 256+ peripheral events (e.g., ADC EOC → DMA trigger → GPT start) without CPU intervention. |
| RMII Ethernet interface | Integrated 10/100 Mbps Ethernet MAC with RMII pinout; requires external PHY but no external MII bus logic or glue. |
| 10-channel SCI with FIFO | Each SCI channel includes independent 16-deep FIFOs for full-duplex UART, SPI, I²C, and smart card protocols - reducing interrupt load by >70% vs. byte-level polling. |
Applications
| Industrial Gateway | Secure Edge Node |
|---|---|
Use Scenario: Protocol translation between Modbus RTU field devices and cloud MQTT over TLS via cellular/Wi-Fi. IC Role / Device Role / Timing Role: Main application processor handling TCP/IP stack, TLS offload via SCE9, real-time scheduling of fieldbus tasks using GPT32 timers. Use Value: Dual CAN FD and Ethernet enable concurrent legacy fieldbus and modern IP network connectivity; 200 MHz core ensures <50 µs latency for time-critical control loops. | Use Scenario: Tamper-evident remote sensor node collecting vibration, temperature, and humidity data for predictive maintenance. IC Role / Device Role / Timing Role: Secure data acquisition controller with encrypted local storage (data flash), authenticated OTA updates, and low-power AGT-driven wake-on-event sampling. Use Value: SCE9 accelerates AES-GCM encryption of sensor payloads; TrustZone isolates key storage from application firmware; VBATT-backed RTC enables precise timestamping across power cycles. |
| Human-Machine Interface (HMI) | Medical Data Logger |
Use Scenario: Touch-enabled panel PC for factory floor operator interface with graphical display and safety-critical alarm handling. IC Role / Device Role / Timing Role: HMI controller managing capacitive touch (CTSU), display refresh via QSPI-connected framebuffer, and real-time alarm response via IRQn-DS deep-standby wake sources. Use Value: CTSU supports up to 15 electrodes with noise immunity; 512 KB SRAM accommodates double-buffered GUI rendering; AGT timers provide sub-millisecond touch response. | Use Scenario: Portable diagnostic device logging ECG waveforms with secure patient ID binding and HIPAA-compliant audit trail. IC Role / Device Role / Timing Role: Medical-grade data acquisition unit performing 12-bit ADC sampling at 5 Msps (interleaved), timestamping with RTC calendar mode, and encrypting records before SDHI write. Use Value: Dual ADC12 units enable simultaneous multi-channel acquisition; SDHI supports SDXC cards for >10-hour waveform storage; SCE9 signs logs with private key stored in secure enclave. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Arm Cortex-M33 microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R7FA6M5AH2CBG | 2 MB code flash (vs. 1.5 MB), same 176-pin FBGA, identical peripherals and security features. | Preferred where larger firmware image size or future-proofing for feature expansion is required. | Select when firmware growth headroom exceeds 512 KB or dual-bank update reliability demands maximum flash endurance margin. |
| R7FA6M5AG3CFC | Same 1.5 MB flash, but 176-pin LQFP (24 mm × 24 mm, 0.5 mm pitch) and extended -40°C to +105°C temperature range. | Suitable for high-temperature industrial enclosures where FBGA rework is impractical. | Choose for ease of prototyping, manual soldering, or thermal environments exceeding +85°C ambient. |
Compared with R7FA6M5AG2CBG, R7FA6M5AH2CBG offers higher flash density for complex protocol stacks, while R7FA6M5AG3CFC trades FBGA miniaturization for LQFP manufacturability and wider thermal tolerance - neither is pin-compatible, requiring PCB redesign.
Availability
R7FA6M5AG2CBG is available at Aetrix Electronics and suitable for industrial gateways, secure edge nodes, HMI panels, and medical data loggers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for R7FA6M5AG2CBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RA6M5 Group targets high-performance, secure industrial and edge applications, integrating Arm TrustZone, hardware crypto acceleration, and rich connectivity to replace discrete security + MCU + PHY combinations with a single-chip solution.
FAQ
What is the maximum operating frequency and core architecture of the R7FA6M5AG2CBG?
The R7FA6M5AG2CBG features an Arm Cortex-M33 core operating at a maximum frequency of 200 MHz. It implements the Armv8-M architecture with security extensions, including TrustZone, and uses the Protected Memory System Architecture (PMSAv8) with separate secure and non-secure MPU regions. This architecture enables hardware-enforced isolation between trusted and untrusted software domains within the R7FA6M5AG2CBG.
Does the R7FA6M5AG2CBG support dual-bank flash operation and background programming?
Yes, the R7FA6M5AG2CBG supports dual-bank flash operation with background programming and SWAP functionality. Its 1.5 MB code flash is organized into two banks, allowing one bank to be executed while the other is programmed or erased - enabling seamless firmware updates without system interruption. This capability is natively supported by the R7FA6M5AG2CBG's flash control unit and documented in the R01DS0366EJ0150 datasheet.
What package type and pin count does the R7FA6M5AG2CBG use?
The R7FA6M5AG2CBG uses a 176-pin Fine-Pitch Ball Grid Array (FBGA) package with part code PLBG0176GF-A, measuring 13 mm × 13 mm with 0.8 mm pitch and Sn (tin) terminal finish. This package provides 132 general-purpose I/O pins, 17 of which are 5-V tolerant, and is qualified for industrial temperature operation from -40°C to +85°C - matching the R7FA6M5AG2CBG's specified operating range.
Which communication interfaces are integrated into the R7FA6M5AG2CBG?
The R7FA6M5AG2CBG integrates Ethernet MAC (RMII), USB 2.0 High-Speed and Full-Speed modules, two CAN FD controllers, Quad and Octa SPI, SD/MMC Host Interface (SDHI), Serial Sound Interface Enhanced (SSIE), Consumer Electronics Control (CEC), ten Serial Communications Interfaces (SCI), three I²C buses, and two standard SPI channels. All interfaces are directly accessible via dedicated pins on the R7FA6M5AG2CBG FBGA package and supported by hardware accelerators like the Event Link Controller.
How does the Secure Crypto Engine (SCE9) in the R7FA6M5AG2CBG enhance system security?
The Secure Crypto Engine 9 (SCE9) in the R7FA6M5AG2CBG provides hardware-accelerated symmetric (AES-128/256), asymmetric (RSA-2048/4096, ECC-256/384), and hash (SHA-224/256) operations, plus a 128-bit unique ID and tamper detection circuitry. It operates within the TrustZone-secured environment, isolating key generation, storage, and cryptographic processing from the non-secure application firmware running on the R7FA6M5AG2CBG - preventing software-based key extraction or side-channel attacks.
R7FA6M5AG2CBG#BC0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 176-LFBGA
- Series:
- RA6M5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 200MHz
- Connectivity:
- CANbus, Ethernet, I2C, MMC/SD, SCI, SPI, QSPI, UART/USART, USB
- Peripherals:
- Crypto - AES, DMA, LVD, POR, PWM, RSA, SHA, Temp Sensor, WDT
- Number of I/O:
- 132
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 29x12b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R7FA6M5AG2CBG#BC0 FAQ
1.How can I place an order for R7FA6M5AG2CBG#BC0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R7FA6M5AG2CBG#BC0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R7FA6M5AG2CBG#BC0 reliable?
The price and inventory of R7FA6M5AG2CBG#BC0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R7FA6M5AG2CBG#BC0 is usually 5 days.
3.What payment methods are accepted for R7FA6M5AG2CBG#BC0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R7FA6M5AG2CBG#BC0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R7FA6M5AG2CBG#BC0?
R7FA6M5AG2CBG#BC0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R7FA6M5AG2CBG#BC0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R7FA6M5AG2CBG#BC0?
For technical support, including R7FA6M5AG2CBG#BC0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R7FA6M5AG2CBG#BC0 requirements.
6.How does Aetrix verify that R7FA6M5AG2CBG#BC0 is sourced from the original manufacturer or authorized distributors?
All R7FA6M5AG2CBG#BC0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R7FA6M5AG2CBG#BC0 meets industry standards.
7.What is the process for return or replacement of R7FA6M5AG2CBG#BC0?
All R7FA6M5AG2CBG#BC0 units undergo pre-shipment inspection (PSI). If there is an issue with R7FA6M5AG2CBG#BC0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R7FA6M5AG2CBG#BC0 part is unused and in its original packaging.
Return procedure for R7FA6M5AG2CBG#BC0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R7FA6M5AG2CBG#BC0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

