Renesas R7FA6M5AG3CFP#AA0
- Part No.:
- R7FA6M5AG3CFP#AA0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
R7FA6M5AG3CFP#AA0.pdf
- Description:
- IC MCU 32BIT 1.5MB FLSH 100LFQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,339
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R7FA6M5AG3CFP#AA0 from Renesas is a high-performance 32-bit Arm Cortex-M33 microcontroller operating at up to 200 MHz, featuring 1.5 MB dual-bank code flash, 8 KB data flash, 512 KB SRAM with ECC/parity, integrated Ethernet MAC, USB 2.0 High-Speed and Full-Speed, dual CAN FD, QSPI/OSPI, and Secure Crypto Engine (SCE9) with TrustZone support. It targets industrial gateways requiring secure connectivity, real-time control, and deterministic communication.
For engineers reviewing the R7FA6M5AG3CFP#AA0 datasheet, R7FA6M5AG3CFP#AA0 pinout, R7FA6M5AG3CFP#AA0 application, or R7FA6M5AG3CFP#AA0 equivalent, key selection considerations include its -40°C to +105°C LQFP-100 package, 1.5 MB flash capacity, dual CAN FD interfaces, Ethernet MAC with RMII support, and hardware-accelerated cryptographic primitives (AES/RSA/ECC/SHA256).
Technical Context
The R7FA6M5AG3CFP#AA0 implements Armv8-M architecture with TrustZone security extension, enabling strict isolation between secure and non-secure firmware execution environments. Its memory subsystem includes dual-bank flash supporting background programming and SWAP operations, plus 512 KB SRAM partitioned into 448 KB parity-protected and 64 KB ECC-protected regions.
Connectivity is centered on two independent CAN FD controllers (16 TX/RX buffers each), an RMII-capable Ethernet MAC/DMA controller, USBHS/USBFS modules with internal transceivers, and high-speed serial memory interfaces - QSPI for quad-flash and OSPI for octal-flash devices - all accessible without CPU intervention via ELC-triggered DMA transfers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | Arm Cortex-M33 @ 200 MHz with TrustZone, MPU_S/MPU_NS (8 regions each) |
| Memory | 1.5 MB dual-bank code flash (background/SWAP), 8 KB data flash (100k P/E cycles), 512 KB SRAM (448 KB parity + 64 KB ECC) |
| Operating Temp | -40°C to +105°C - qualified for extended industrial temperature operation |
| Package | 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch) with 75 I/O pins and 14 5-V-tolerant inputs |
| Connectivity | Dual CAN FD (ISO 11898-1), Ethernet MAC (RMII only), USB 2.0 HS/FS, QSPI, OSPI, SDHI, SCI×10, IIC×3, SPI×2 |
| Security | Secure Crypto Engine 9 (AES-128/256, RSA-2048/4096, ECC-256/384, SHA224/256), tamper detection, 128-bit unique ID |
| Analog | ADC12×2 (13/16 ch, 5 Msps interleaved), DAC12×2, TSN, CTSU (12 electrodes) |
Pinout & Package
100-pin LQFP (PLQP0100KB-B), 14 mm × 14 mm, 0.5 mm pitch, -40°C to +105°C operating range. Features 75 general-purpose I/O pins, 14 5-V-tolerant inputs, 1 dedicated VBATT pin for RTC backup, and RMII-compliant Ethernet interface pins (TXD0/TXD1/TXEN/RXD0/RXD1/CRS_DV/REF_CLK).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Core logic power (2.7–3.6 V); decoupling required per datasheet layout guidelines |
| VBATT | Battery backup supply | Enables RTC calendar and backup SRAM retention during main power loss |
| XTAL / EXTAL | Main clock oscillator interface | Supports 8–24 MHz crystal or external clock source for system timing |
| XCIN / XCOUT | Sub-clock oscillator interface | 32.768 kHz crystal connection for RTC and low-power wake-up timing |
| MD | Mode configuration | Defines boot mode (single-chip vs. SCI/USB boot) at reset assertion |
| RES | Reset input | Active-low asynchronous reset pin; internal pull-up enabled by default |
| TXD0–TXD1, RXD0–RXD1, TXEN, CRS_DV, REF_CLK | Ethernet RMII interface | Direct connection to PHY without external glue logic; supports 10/100 Mbps |
| CANFD0_TX / CANFD0_RX / CANFD1_TX / CANFD1_RX | CAN FD physical layer interface | Differential signaling pairs; require external CAN transceivers per ISO 11898-2 |
| QSPI_IO0–QSPI_IO3, QSPI_CLK, QSPI_CS | Quad SPI memory interface | Direct connection to serial NOR flash; supports XIP and execute-in-place capability |
| OSPI_IO0–OSPI_IO7, OSPI_CLK, OSPI_CS | Octa SPI memory interface | High-bandwidth interface for OctaFlash/OctaRAM; enables >100 MB/s read throughput |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with SWAP | Enables seamless firmware updates with zero downtime - critical for industrial field-deployed devices |
| Hardware crypto acceleration | SCE9 delivers AES-256 encryption at >100 Mbps, RSA-4096 signing in <12 ms, eliminating software-only bottlenecks |
| TrustZone-enforced memory isolation | Allows secure bootloader, key storage, and OTA update verification in isolated secure world while running Linux/RTOS in non-secure world |
| Event Link Controller (ELC) | Enables autonomous peripheral chaining (e.g., ADC trigger → DMA transfer → interrupt) without CPU involvement, reducing latency and power |
| RMII Ethernet + dual CAN FD | Provides redundant industrial networking: Ethernet for backbone connectivity and CAN FD for deterministic local machine control |
Applications
| Industrial Gateway | Secure Edge Node |
|---|---|
Use Scenario: Aggregating data from Modbus RTU/ASCII field devices over RS-485 and forwarding to cloud via Ethernet/Wi-Fi. IC Role / Device Role / Timing Role: Central protocol translator and secure edge compute node with real-time scheduling and encrypted TLS tunneling. Use Value: Dual CAN FD handles multiple PLC networks simultaneously; SCE9 accelerates TLS 1.2/1.3 handshake and certificate validation. | Use Scenario: Remote monitoring of energy meters, environmental sensors, and motor drives in distributed substations. IC Role / Device Role / Timing Role: Trusted execution environment for firmware integrity checks, secure boot, and tamper-evident logging using RTC-backed timestamps. Use Value: TrustZone isolates secure boot loader and key management; VBATT-backed RTC ensures accurate event time-stamping during brownouts. |
| Motor Control Hub | HMI Controller |
Use Scenario: Coordinating multi-axis servo drives in packaging machinery using fieldbus and PWM outputs. IC Role / Device Role / Timing Role: Real-time motion controller with GPT32 timers generating synchronized 3-phase PWM waveforms and AGT timers managing encoder sampling. Use Value: GPT32×4 + GPT16×6 provide 10 independent PWM channels; ELC links ADC triggers to DMA for jitter-free current sensing. | Use Scenario: Touch-enabled operator panel with graphical display, audio feedback, and SD card-based firmware updates. IC Role / Device Role / Timing Role: Human-machine interface processor managing capacitive touch (CTSU), SSIE audio playback, and SDHI-based storage. Use Value: CTSU supports 12 electrodes for button/slider/gesture recognition; SDHI enables hot-swappable field updates without device shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Arm Cortex-M33 microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R7FA6M5AH3CFP#AA0 | 2 MB code flash (vs. 1.5 MB), identical peripherals, same LQFP-100 package and temp grade | Required when firmware image size exceeds 1.5 MB or dual-bank SWAP is needed for larger OTA payloads | Select R7FA6M5AH3CFP#AA0 if future firmware growth or enhanced redundancy requirements demand extra flash headroom. |
| R7FA6M5BG3CFP#AA0 | 1 MB code flash, same 8 KB data flash, 512 KB SRAM, identical package and temperature rating | Suitable for cost-sensitive designs where feature set matches but flash footprint is smaller | Choose R7FA6M5BG3CFP#AA0 for legacy migration or simplified BOMs where full 1.5 MB flash is unused. |
Compared with R7FA6M5AG3CFP#AA0, R7FA6M5AH3CFP#AA0 offers higher flash density for complex protocol stacks, while R7FA6M5BG3CFP#AA0 reduces cost and power in resource-constrained edge nodes - all share identical pinout, peripheral count, and security architecture.
Availability
R7FA6M5AG3CFP#AA0 is available at Aetrix Electronics and suitable for industrial gateways, secure edge nodes, motor control hubs, and HMI controllers requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for R7FA6M5AG3CFP#AA0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RA6M5 Group, including R7FA6M5AG3CFP#AA0, is designed for secure, high-performance industrial and IoT edge applications demanding real-time responsiveness, robust connectivity, and hardware-enforced trust.
FAQ
What is the maximum operating frequency of the R7FA6M5AG3CFP#AA0?
The R7FA6M5AG3CFP#AA0 operates at a maximum frequency of 200 MHz using its Arm Cortex-M33 core. This speed is achieved with the PLL clock source and requires proper decoupling and thermal management per the datasheet layout guidelines. The R7FA6M5AG3CFP#AA0 maintains this frequency across its full -40°C to +105°C operating temperature range when powered within the 2.7–3.6 V VCC specification.
Does the R7FA6M5AG3CFP#AA0 support Ethernet connectivity?
Yes, the R7FA6M5AG3CFP#AA0 integrates an Ethernet MAC controller compliant with IEEE 802.3, supporting 10/100 Mbps operation in RMII mode. It requires an external PHY IC and does not include a built-in PHY. The R7FA6M5AG3CFP#AA0 provides dedicated RMII pins (TXD0/TXD1/TXEN/RXD0/RXD1/CRS_DV/REF_CLK) and connects to the Ethernet DMA controller (EDMAC) for zero-copy packet handling.
How much flash memory does the R7FA6M5AG3CFP#AA0 have, and what type is it?
The R7FA6M5AG3CFP#AA0 contains 1.5 MB of on-chip code flash memory implemented as dual-bank flash, enabling background programming and SWAP operations for reliable firmware updates. It also includes 8 KB of data flash memory rated for 100,000 program/erase cycles, optimized for parameter storage and wear-leveling. Both flash types are accessible under TrustZone-secured memory protection.
What security features are integrated into the R7FA6M5AG3CFP#AA0?
The R7FA6M5AG3CFP#AA0 integrates the Secure Crypto Engine 9 (SCE9) with hardware acceleration for AES-128/256, RSA-2048/4096, ECC-256/384, and SHA224/256. It also includes Arm TrustZone for hardware-enforced secure/non-secure world separation, tamper detection pins, secure key management, and 128-bit unique device ID. These features are fully operational in the R7FA6M5AG3CFP#AA0's -40°C to +105°C industrial grade.
Which package and pin count does the R7FA6M5AG3CFP#AA0 use?
The R7FA6M5AG3CFP#AA0 uses a 100-pin LQFP package (PLQP0100KB-B), measuring 14 mm × 14 mm with 0.5 mm pitch. It provides 75 general-purpose I/O pins, 14 of which are 5-V tolerant, along with dedicated pins for RMII Ethernet, dual CAN FD, QSPI, OSPI, SDHI, and USB HS/FS. This package is rated for -40°C to +105°C operation.
R7FA6M5AG3CFP#AA0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 100-LQFP
- Series:
- RA6M5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit Single-Core
- Speed:
- 200MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- Capacitive Touch, Crypto - AES, DMA, LVD, POR, PWM, RSA, SHA, Temp Sensor, WDT
- Number of I/O:
- 75
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 20x12b SAR; D/A 2x12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R7FA6M5AG3CFP#AA0 FAQ
1.How can I place an order for R7FA6M5AG3CFP#AA0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R7FA6M5AG3CFP#AA0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R7FA6M5AG3CFP#AA0 reliable?
The price and inventory of R7FA6M5AG3CFP#AA0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R7FA6M5AG3CFP#AA0 is usually 5 days.
3.What payment methods are accepted for R7FA6M5AG3CFP#AA0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R7FA6M5AG3CFP#AA0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R7FA6M5AG3CFP#AA0?
R7FA6M5AG3CFP#AA0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R7FA6M5AG3CFP#AA0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R7FA6M5AG3CFP#AA0?
For technical support, including R7FA6M5AG3CFP#AA0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R7FA6M5AG3CFP#AA0 requirements.
6.How does Aetrix verify that R7FA6M5AG3CFP#AA0 is sourced from the original manufacturer or authorized distributors?
All R7FA6M5AG3CFP#AA0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R7FA6M5AG3CFP#AA0 meets industry standards.
7.What is the process for return or replacement of R7FA6M5AG3CFP#AA0?
All R7FA6M5AG3CFP#AA0 units undergo pre-shipment inspection (PSI). If there is an issue with R7FA6M5AG3CFP#AA0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R7FA6M5AG3CFP#AA0 part is unused and in its original packaging.
Return procedure for R7FA6M5AG3CFP#AA0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R7FA6M5AG3CFP#AA0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

