Renesas R7FA6M5BG3CFB#BA0
- Part No.:
- R7FA6M5BG3CFB#BA0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
R7FA6M5BG3CFB#BA0.pdf
- Description:
- MCU RA6 ARM CM33 200MHZ 1.5M/512
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R7FA6M5BG3CFB#BA0 from Renesas is a high-performance 32-bit Arm Cortex-M33 microcontroller operating at up to 200 MHz, featuring 1.5 MB code flash, 8 KB data flash, and 512 KB SRAM with ECC/parity. It integrates dual CAN FD controllers, Ethernet MAC, USB 2.0 High-Speed/Full-Speed, QSPI/OSPI, SDHI, and Secure Crypto Engine (SCE9) with TrustZone for secure IoT edge nodes and industrial gateways.
For engineers reviewing the R7FA6M5BG3CFB#BA0 datasheet, R7FA6M5BG3CFB#BA0 pinout, R7FA6M5BG3CFB#BA0 application, or R7FA6M5BG3CFB#BA0 equivalent, key selection criteria include its -40°C to +105°C operation, 144-pin LQFP package, dual-bank flash for robust OTA updates, hardware-accelerated AES/RSA/ECC, and integrated CTSU for touch HMI in space-constrained industrial control panels.
Technical Context
The R7FA6M5BG3CFB#BA0 implements Armv8-M with TrustZone, enabling secure/non-secure world isolation across memory regions (flash/SRAM/data flash), peripherals, and MPU configurations. Its dual CAN FD channels support ISO 11898-1 frames with 16 transmit/receive buffers per channel, while the ETHERC/EDMAC pair enables zero-CPU packet handling via DMA.
Security is enforced through SCE9 - delivering AES-128/256, RSA-2048/4096, ECC-256/384, SHA-256, and tamper detection - tightly coupled with TrustZone's peripheral attribution and lifecycle management. Clocking includes PLL/PLL2, HOCO/MOCO/LOCO oscillators, and CAC for real-time frequency accuracy monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M33 @ 200 MHz with TrustZone and dual MPU (8 secure + 8 non-secure regions) |
| Memory | 1.5 MB dual-bank code flash (SWAP/background operation), 8 KB data flash (100k P/E cycles), 512 KB SRAM with ECC/parity |
| Connectivity | Dual CAN FD (16 TX/RX buffers each), Ethernet MAC (RMII), USB 2.0 HS/FS, QSPI/OSPI, SDHI, 10× SCI, 3× I²C, 2× SPI |
| Analog | Two 12-bit ADCs (ADC12): 13+16 channels, 5 Msps interleaved; two 12-bit DACs (DAC12); on-die temperature sensor (TSN) |
| Security | Secure Crypto Engine 9 (AES/RSA/ECC/SHA256), 128-bit unique ID, tamper pins, power analysis resistance, TrustZone-peripheral attribution |
| Package & Temp | 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch), industrial grade (-40°C to +105°C) |
| Power & Timing | VCC: 2.7–3.6 V; RTC with calendar (2000–2099), VBATT backup; 6× AGT timers, 4× GPT32, 6× GPT16, ELC event linking |
Pinout & Package
144-pin LQFP (PLQP0144KA-B), 20 mm × 20 mm, 0.5 mm pitch, with 109 I/O pins, 21 5-V-tolerant inputs, 110 pull-up resistors, and N-ch open-drain outputs on all I/Os.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dedicated analog/digital power domains; decoupling required per datasheet layout guidelines |
| XTAL / EXTAL | Main clock oscillator interface | Supports 8–24 MHz crystal; external clock input option for synchronous system timing |
| XCIN / XCOUT | Sub-clock oscillator | 32.768 kHz crystal connection for RTC calendar and low-power wake-up |
| MD | Mode control | Configures single-chip vs. SCI/USB boot mode; must be stable during reset release |
| RES | Reset input | Active-low asynchronous reset; internal POR/LVD ensures reliable initialization |
| VBATT | Battery backup | Supplies RTC, SOSC, and backup RAM during main power loss |
| TXD0–TXD9 / RXD0–RXD9 | SCI serial I/O | 10 independent UART/SCI channels with FIFO, baud rate generator, and Manchester support |
| CANFD0_TX / CANFD0_RX / CANFD1_TX / CANFD1_RX | CAN FD physical interface | Dedicated differential pairs per channel; supports classical CAN and CAN FD up to 5 Mbps |
| ETH_MDIO / ETH_MDC / ETH_RXD0–3 / ETH_TXD0–3 / ETH_CRS_DV / ETH_COL / ETH_REF_CLK | Ethernet PHY interface | RMII-compliant 2-line interface; requires external PHY (e.g., LAN8742A) for IEEE 802.3 compliance |
| USBHS_DP / USBHS_DM / USBFS_DP / USBFS_DM | USB differential pairs | Separate high-speed (480 Mbps) and full-speed (12 Mbps) transceivers; no external PHY needed |
| QSPI_IO0–3 / OSPI_IO0–7 | Quad/Octa SPI data lines | Direct memory-mapped interface to external flash; OSPI supports OctaFlash/OctaRAM at up to 200 MHz |
| SD0_CMD / SD0_CLK / SD0_DAT0–3 | SD/MMC host interface | 4-bit SDHC/SDXC support; compliant with SD Host License Agreement (SD HALA) |
| CTSU_S0–S14 | Capacitive touch sensing | 15-channel CTSU for button/slider/wheel HMI; supports self- and mutual-capacitance modes |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with SWAP operation | Enables seamless over-the-air (OTA) firmware updates without application interruption or external memory |
| Hardware crypto acceleration (SCE9) | Offloads AES-128/256 encryption, RSA-2048 signing, and SHA-256 hashing from CPU, reducing latency and power |
| TrustZone-enabled peripheral security | Allows secure boot, encrypted key storage, and isolated secure firmware execution with hardware-enforced boundaries |
| Integrated CTSU with 15 channels | Eliminates need for external touch controller IC; supports proximity, gesture, and waterproof touch in industrial HMI |
| Event Link Controller (ELC) | Permits direct peripheral-to-peripheral triggering (e.g., ADC conversion → DMA transfer → GPT capture) without CPU intervention |
| Low-power AGT timers with VBATT support | 6 independent 16-bit timers operate in Deep Software Standby mode using sub-clock oscillator for battery-backed scheduling |
Applications
| Industrial Gateway | Secure Edge Node |
|---|---|
Use Scenario: Protocol translation between Modbus RTU field devices and cloud MQTT over Ethernet/USB. IC Role / Device Role / Timing Role: Central MCU managing dual CAN FD buses, Ethernet MAC, USB host, and secure TLS stack via SCE9. Use Value: Dual-bank flash enables fail-safe firmware updates; TrustZone isolates secure key storage from application logic. | Use Scenario: Tamper-resistant sensor aggregator in smart metering with local anomaly detection and encrypted reporting. IC Role / Device Role / Timing Role: Secure processing node running RTOS with SCE9-accelerated AES-GCM encryption and RTC-triggered sampling. Use Value: Tamper pins detect physical intrusion; VBATT-backed RTC maintains time sync during power outage. |
| Human-Machine Interface Panel | Motor Control Gateway |
Use Scenario: Touch-enabled operator panel for PLC-controlled machinery with real-time status visualization. IC Role / Device Role / Timing Role: HMI controller driving LCD via parallel bus, reading capacitive buttons via CTSU, and communicating via CAN FD to motion controllers. Use Value: Integrated CTSU reduces BOM cost; 109 GPIOs support flexible display interface and I/O expansion. | Use Scenario: BLDC motor gateway coordinating multiple drives via CAN FD while monitoring current/voltage via ADC12. IC Role / Device Role / Timing Role: Real-time motor supervisor using GPT32 for PWM generation, AGT for precise commutation timing, and dual ADC12 for simultaneous phase current sampling. Use Value: 5 Msps interleaved ADC enables accurate current reconstruction; ELC links ADC end-of-conversion to GPT reload for jitter-free timing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Arm Cortex-M33 microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R7FA6M5BH3CFB#BA0 | 2 MB code flash (vs. 1.5 MB), same package/peripherals/security features | Suitable where larger firmware image size or future feature expansion is required | Select when bootloader, secure boot assets, and application code exceed 1.5 MB footprint |
| R7FA6M5BG3CFC#AA0 | 176-pin LQFP (24 mm × 24 mm), 132 I/Os (vs. 109), same memory/peripherals | Better suited for designs requiring higher I/O count or external bus interface (ECBIU/QSPI/OSPI) | Choose when additional GPIOs, parallel bus access, or larger PCB layout margin is available |
Compared with R7FA6M5BH3CFB#BA0 and R7FA6M5BG3CFC#AA0, the R7FA6M5BG3CFB#BA0 offers optimal balance of memory capacity, I/O count, and thermal performance in compact 144-pin LQFP - ideal for cost-sensitive, space-constrained industrial gateways requiring CAN FD and Ethernet but not maximum flash or pin count.
Availability
R7FA6M5BG3CFB#BA0 is available at Aetrix Electronics and suitable for industrial automation gateways, secure edge IoT nodes, human-machine interface panels, and motor control systems requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for R7FA6M5BG3CFB#BA0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and enterprise markets.
The RA6M5 Group targets high-performance, secure industrial and IoT edge applications, combining Arm Cortex-M33 with integrated connectivity (CAN FD, Ethernet, USB), advanced analog, and hardware security (SCE9 + TrustZone) to accelerate certified device development.
FAQ
What is the maximum operating frequency and core architecture of the R7FA6M5BG3CFB#BA0?
The R7FA6M5BG3CFB#BA0 features an Arm Cortex-M33 core operating at up to 200 MHz, implementing the Armv8-M architecture with Security Extension (TrustZone). It includes dual Memory Protection Units (MPUs) - one secure and one non-secure - each supporting eight memory regions, enabling robust software isolation for secure firmware execution and peripheral access control in the R7FA6M5BG3CFB#BA0.
Does the R7FA6M5BG3CFB#BA0 support CAN FD, and how many channels are available?
Yes, the R7FA6M5BG3CFB#BA0 supports CAN with Flexible Data-rate (CAN FD) with two independent channels compliant with ISO 11898-1. Each channel provides 16 dedicated transmit buffers and 16 receive buffers, enabling concurrent high-bandwidth communication with legacy CAN and CAN FD nodes - a key capability confirmed in the R7FA6M5BG3CFB#BA0 datasheet section 1.4 and Table 1.14.
What security features does the R7FA6M5BG3CFB#BA0 integrate beyond Arm TrustZone?
Beyond Arm TrustZone, the R7FA6M5BG3CFB#BA0 integrates the Secure Crypto Engine 9 (SCE9), which provides hardware-accelerated symmetric (AES-128/256), asymmetric (RSA-2048/4096, ECC-256/384), and hash (SHA-256) operations. It also includes tamper detection pins, power analysis resistance, a 128-bit unique ID, and device lifecycle management - all documented in the R7FA6M5BG3CFB#BA0 datasheet sections 1.1 and 1.4.
What is the package type and pin count of the R7FA6M5BG3CFB#BA0?
The R7FA6M5BG3CFB#BA0 uses a 144-pin LQFP package (PLQP0144KA-B), measuring 20 mm × 20 mm with 0.5 mm pitch. It provides 109 general-purpose I/O pins, 21 of which are 5-V tolerant, along with dedicated power, clock, reset, and peripheral interface pins - as specified in the R7FA6M5BG3CFB#BA0 part numbering scheme (Figure 1.2) and Table 1.13 of the datasheet.
Does the R7FA6M5BG3CFB#BA0 include integrated analog peripherals, and what are their specifications?
Yes, the R7FA6M5BG3CFB#BA0 integrates two 12-bit successive approximation ADC units (ADC12): Unit 0 supports up to 13 channels, Unit 1 supports up to 16 channels, with three shared analog input pins (AN000/AN100, etc.), enabling up to 26 total analog inputs. It also includes two 12-bit DACs (DAC12) and an on-die temperature sensor (TSN) - all confirmed in Table 1.9 and Figure 1.1 of the R7FA6M5BG3CFB#BA0 datasheet.
R7FA6M5BG3CFB#BA0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 144-LQFP
- Series:
- RA6M5
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 200MHz
- Connectivity:
- CANbus, EBI/EMI, Ethernet, I2C, MMC/SD, QSPI, SCI, SPI, SSI, UART/USART, USB
- Peripherals:
- Crypto - AES, DMA, LVD, POR, PWM, RSA, SHA, Temp Sensor, WDT
- Number of I/O:
- 109
- Program Memory Size:
- 1.5MB (1.5M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 25x12b SAR; D/A 2x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R7FA6M5BG3CFB#BA0 FAQ
1.How can I place an order for R7FA6M5BG3CFB#BA0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R7FA6M5BG3CFB#BA0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R7FA6M5BG3CFB#BA0 reliable?
The price and inventory of R7FA6M5BG3CFB#BA0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R7FA6M5BG3CFB#BA0 is usually 5 days.
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5.How can I obtain technical support or documentation for R7FA6M5BG3CFB#BA0?
For technical support, including R7FA6M5BG3CFB#BA0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R7FA6M5BG3CFB#BA0 requirements.
6.How does Aetrix verify that R7FA6M5BG3CFB#BA0 is sourced from the original manufacturer or authorized distributors?
All R7FA6M5BG3CFB#BA0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R7FA6M5BG3CFB#BA0 meets industry standards.
7.What is the process for return or replacement of R7FA6M5BG3CFB#BA0?
All R7FA6M5BG3CFB#BA0 units undergo pre-shipment inspection (PSI). If there is an issue with R7FA6M5BG3CFB#BA0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R7FA6M5BG3CFB#BA0 part is unused and in its original packaging.
Return procedure for R7FA6M5BG3CFB#BA0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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