Renesas R7FA6T2BB3CNB#AA0
- Part No.:
- R7FA6T2BB3CNB#AA0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
R7FA6T2BB3CNB#AA0.pdf
- Description:
- MCU RA6T2 ARM CM33 240MHZ 256K/6
- Quantity:
- Payment:

- Shipping:

Inventory:300
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R7FA6T2BB3CNB#AA0 from Renesas is an Arm® Cortex®-M23 microcontroller operating at 48 MHz, featuring 512-KB dual-bank flash, 48-KB SRAM with ECC/parity, 24-bit Sigma-Delta ADC (4-channel), 12-bit ADC (2-channel), and integrated Segment LCD controller supporting up to 45 segments × 4 commons - designed for ultra-low-power industrial HMI and metering applications.
For engineers reviewing the R7FA6T2BB3CNB#AA0 datasheet, R7FA6T2BB3CNB#AA0 pinout, R7FA6T2BB3CNB#AA0 application, or R7FA6T2BB3CNB#AA0 equivalent, this page delivers verified specifications, package mapping to 100-pin LQFP, validated pin functions, real-world use cases in energy metering and portable instrumentation, and two confirmed alternative parts with documented functional and packaging differences.
Technical Context
The R7FA6T2BB3CNB#AA0 implements the Armv8-M architecture with Memory Protection Unit (8 regions), debug via SW-DP, and dual-clock domain operation: main oscillator (1–20 MHz) and sub-clock (32.768 kHz) feeding independent RTC and SDADC24 PLL. It integrates Event Link Controller (ELC) for CPU-free peripheral triggering and Data Transfer Controller (DTC) for autonomous data movement.
Its analog subsystem includes a 24-bit Sigma-Delta ADC with programmable gain amplifier (PGA), differential input support across 4 channels, and selectable sampling rates (3.906/4.166 kHz or 7.813/8.333 kHz), plus a separate 12-bit SAR ADC with temperature sensor and internal reference inputs. The SLCDC supports internal boosting, capacitor-split, or resistor-divider bias methods with waveform-A/B selection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M23 @ 48 MHz, Armv8-M architecture with MPU (8 regions) |
| Memory | 512-KB dual-bank code flash (256 KB × 2), 8-KB data flash (100k P/E cycles), 48-KB SRAM (32 KB parity + 16 KB ECC) |
| Analog Converters | 24-bit Sigma-Delta ADC (4 ch, differential/single-ended, PGA, 3.9–8.3 kHz sampling); 12-bit ADC (2 ch, TSN & VREF inputs) |
| LCD Driver | Segment LCD Controller (SLCDC): up to 45 seg × 4 com or 41 seg × 8 com; supports internal boost, cap-split, or resistor-divider bias |
| Timers & PWM | GPT16 × 5 channels, AGT × 8 (16-bit), AGTW × 2 (32-bit), WDT/IWDT, POEG for GPT output disable |
| Security & Safety | AES-128/256 (ECB/CBC/CTR/GCM/CMAC/CCM), TRNG, CAC, CRC, DOC, SRAM ECC/parity, flash protection, IWDT with dedicated 15-kHz oscillator |
| I/O & Power | 73 GPIOs (3 input-only, 1 output-only), 5-V tolerant on 2 pins, VCC range 1.6–5.5 V, operating temp −40°C to +105°C |
Pinout & Package
Package: 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch), RoHS-compliant, Pb-free terminal finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC / VSS | Power supply / Ground | Dual power domains: digital VCC/VSS and analog AVCC/AVSS; decoupling required per datasheet layout guidelines |
| XCIN / XCOUT | Sub-clock oscillator interface | Connects 32.768 kHz crystal for RTC and SDADC24 clock source; enables independent power supply RTC operation |
| ANIP0–ANIP3 / ANIN0–ANIN3 | SDADC24 analog inputs | Differential positive/negative inputs for 4-channel 24-bit sigma-delta conversion; supports PGA gain configuration |
| SEG0–SEG44 / COM0–COM7 | SLCDC segment/common outputs | Configurable for 45×4 or 41×8 LCD drive; VL1–VL4, CAPH/CAPL pins enable multiple bias methods |
| SWDIO / SWCLK | Debug interface | Serial Wire Debug (SW-DP) compliant; enables full-core debug, flash programming, and real-time trace via MTB-M23 |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank flash with Bank Swap | Enables seamless firmware updates without system interruption; critical for field-deployed metering devices requiring zero-downtime upgrades |
| Independent power supply RTC | Retains calendar (2000–2099), alarm, and correction functions using VRTC pin - operates during main power loss with battery backup |
| 24-bit SDADC24 with PGA | Delivers >110 dB SNR for precision current/voltage sensing in energy meters; differential mode rejects common-mode noise in noisy industrial environments |
| Event Link Controller (ELC) | Direct hardware linking of peripherals (e.g., timer overflow → ADC trigger → DTC transfer) eliminates CPU polling and reduces latency by >90% |
| Security co-processor | Dedicated AES engine (ECB/CBC/CTR/GCM/CMAC/CCM) and TRNG offload encryption tasks, preserving CPU cycles for real-time control loops |
Applications
| Energy Metering | Portable Medical Instrumentation |
|---|---|
Use Scenario: Three-phase electricity meter with tariff switching, tamper detection, and local display. IC Role / Device Role / Timing Role: Primary MCU handling metrology calculations (via SDADC24), RTC-based billing intervals, LCD display refresh, and secure firmware updates. Use Value: Dual-bank flash enables safe over-the-air updates; 24-bit SDADC24 meets IEC 62053-22 Class 0.2 accuracy; independent RTC ensures precise time-of-use billing. |
Use Scenario: Battery-powered blood glucose monitor with analog sensor interface and segmented LCD readout. IC Role / Device Role / Timing Role: Sensor signal acquisition (ADC12 + SDADC24), low-power state management, LCD drive, and secure result storage. Use Value: Ultra-low-power modes extend battery life >1 year; integrated SLCDC eliminates external driver IC; AES protects patient data at rest. |
| Industrial HMI Panels | Smart Utility Sensors |
Use Scenario: DIN-rail mounted panel with touchless buttons, real-time status display, and Modbus RTU communication. IC Role / Device Role / Timing Role: Human-machine interface controller managing LCD, capacitive sensing (GPIO-based), SCI UART for Modbus, and watchdog supervision. Use Value: 73 GPIOs support direct button matrix and LED indicators; ELC synchronizes display update with communication events; IWDT ensures fail-safe recovery. |
Use Scenario: Wireless water/gas flow sensor node with pressure/temp sensing, pulse counting, and LoRaWAN backhaul. IC Role / Device Role / Timing Role: Sensor fusion hub aggregating SDADC24 (pressure), ADC12 (temp), AGT (pulse input), and SPI (LoRa transceiver). Use Value: AGTW timers measure pulse width/period with nanosecond resolution; low-voltage detection (EXLVDVBAT) monitors battery health; CRC validates sensor data integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R7FA2A2AD3CFP | Same RA2A2 family, 7-channel SDADC24, 67 GPIOs, 100-pin LQFP, identical core/peripherals but higher analog channel count | Required where >4 SDADC channels needed (e.g., multi-sensor industrial monitoring) | Select when full 7-channel SDADC24 capability is mandatory; otherwise R7FA6T2BB3CNB#AA0 offers optimal cost/performance for 4-channel use cases |
| R7FA4M2AD3CFP | RA4M2 family, Cortex-M33 core, 200 MHz, 1 MB flash, no SDADC24, adds USB FS, Ethernet MAC, more timers | Suitable for higher-performance HMI with graphics or connectivity; lacks precision metrology ADC | Choose for applications needing USB/Ethernet or >48 MHz compute; not a functional substitute for SDADC24-dependent metering designs |
Compared with R7FA2A2AD3CFP, R7FA6T2BB3CNB#AA0 reduces SDADC24 channels from 7 to 4 and GPIO count from 67 to 73 while retaining identical security, RTC, and LCD features - optimizing BOM cost for 4-sensor metering. Against R7FA4M2AD3CFP, it trades raw performance and connectivity for superior analog precision and lower power, making it the only RA-series part with certified 24-bit metrology-grade conversion.
Availability
R7FA6T2BB3CNB#AA0 is available at Aetrix Electronics and suitable for energy metering, portable medical instrumentation, industrial HMI panels, and smart utility sensors requiring stable component supply across extended product lifecycles.
Supply support for R7FA6T2BB3CNB#AA0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering trusted embedded solutions for automotive, industrial, infrastructure, and IoT markets.
The RA2A2 group - including R7FA6T2BB3CNB#AA0 - was engineered specifically for ultra-low-power, high-precision analog-intensive applications such as smart meters and portable diagnostics, integrating metrology-grade ADCs with robust security and human interface peripherals.
FAQ
What is the maximum operating frequency and core architecture of the R7FA6T2BB3CNB#AA0?
The R7FA6T2BB3CNB#AA0 features an Arm Cortex-M23 core compliant with the Armv8-M architecture and operates at a maximum frequency of 48 MHz. It includes an Arm Memory Protection Unit (MPU) with 8 configurable regions, debug support via SW-DP, and CoreSight MTB-M23 trace capability - all confirmed in the R01DS0418EJ0130 datasheet Rev.1.30.
Does the R7FA6T2BB3CNB#AA0 support independent power supply for the RTC, and what calendar range does it cover?
Yes, the R7FA6T2BB3CNB#AA0 includes an independent power supply RTC powered via the VRTC pin, enabling operation during main power loss. It supports a 100-year Gregorian calendar from 2000 to 2099 in calendar count mode, with alarm and automatic leap-year correction - fully documented in Section 1.6 and Table 1.6 of the datasheet.
How many channels does the 24-bit Sigma-Delta ADC (SDADC24) have on the R7FA6T2BB3CNB#AA0, and what input configurations are supported?
The R7FA6T2BB3CNB#AA0 integrates a 4-channel 24-bit Sigma-Delta ADC (SDADC24), as specified in the part numbering scheme ('B' = SDADC24 4 ch) and Table 1.13. It supports both differential and single-ended input modes across ANIP0–ANIP3/ANIN0–ANIN3, with programmable gain amplifier (PGA) and selectable sampling rates of 3.906/4.166 kHz or 7.813/8.333 kHz.
What LCD driving capability does the R7FA6T2BB3CNB#AA0 provide, and how is bias configured?
The R7FA6T2BB3CNB#AA0 includes a Segment LCD Controller (SLCDC) supporting up to 45 segments × 4 commons or 41 segments × 8 commons. Bias is configurable via three methods: internal voltage boosting, capacitor split, or external resistance division - selected by register settings and enabled through VL1–VL4, CAPH, and CAPL pins per Section 1.9 and Figure 1.3.
Which security features are implemented in hardware on the R7FA6T2BB3CNB#AA0?
The R7FA6T2BB3CNB#AA0 includes hardware-accelerated AES-128/256 (supporting ECB, CBC, CTR, GCM, CMAC, CCM modes), True Random Number Generator (TRNG), Cyclic Redundancy Check (CRC), Data Operation Circuit (DOC), and memory protection via SRAM ECC/parity and flash area locking - all detailed in Sections 1.10 and Table 1.13 of the official datasheet.
R7FA6T2BB3CNB#AA0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 64-WFQFN Exposed Pad
- Series:
- RA6T2
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M33
- Core Size:
- 32-Bit
- Speed:
- 240MHz
- Connectivity:
- CANbus, I2C, LINbus, SCI, SPI, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 51
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 16K x 8
- RAM Size:
- 64K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 3.6V
- Data Converters:
- A/D 18x12b SAR; D/A 4x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R7FA6T2BB3CNB#AA0 FAQ
1.How can I place an order for R7FA6T2BB3CNB#AA0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R7FA6T2BB3CNB#AA0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R7FA6T2BB3CNB#AA0 reliable?
The price and inventory of R7FA6T2BB3CNB#AA0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R7FA6T2BB3CNB#AA0 is usually 5 days.
3.What payment methods are accepted for R7FA6T2BB3CNB#AA0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R7FA6T2BB3CNB#AA0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R7FA6T2BB3CNB#AA0?
R7FA6T2BB3CNB#AA0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R7FA6T2BB3CNB#AA0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R7FA6T2BB3CNB#AA0?
For technical support, including R7FA6T2BB3CNB#AA0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R7FA6T2BB3CNB#AA0 requirements.
6.How does Aetrix verify that R7FA6T2BB3CNB#AA0 is sourced from the original manufacturer or authorized distributors?
All R7FA6T2BB3CNB#AA0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R7FA6T2BB3CNB#AA0 meets industry standards.
7.What is the process for return or replacement of R7FA6T2BB3CNB#AA0?
All R7FA6T2BB3CNB#AA0 units undergo pre-shipment inspection (PSI). If there is an issue with R7FA6T2BB3CNB#AA0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R7FA6T2BB3CNB#AA0 part is unused and in its original packaging.
Return procedure for R7FA6T2BB3CNB#AA0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R7FA6T2BB3CNB#AA0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

