Renesas R9A06G032NGBG#AC1

Overview

R9A06G032NGBG#AC1 from Renesas is a dual-core Arm Cortex-A7 (500 MHz) + Cortex-M3 (125 MHz) industrial communication SoC with integrated 6 MB ECC SRAM, dual Gigabit Ethernet MACs, Advanced 5-Port Switch (A5PSW), EtherCAT Slave Controller (3 ports), SercosIII Slave Controller (2 ports), and PRP/HSR redundancy support per IEC 62439-3 Ed2.0–2012. It targets real-time industrial Ethernet gateways and protocol-converged controllers.

For engineers reviewing the R9A06G032NGBG#AC1 datasheet, R9A06G032NGBG#AC1 pinout, R9A06G032NGBG#AC1 application, or R9A06G032NGBG#AC1 equivalent, key selection criteria include dual-A7/M3 co-processing capability, on-chip 6 MB ECC SRAM, A5PSW QoS and IEEE 1588 support, EtherCAT/SercosIII concurrency limits, and BGA-400 package compatibility with 170 GPIOs and DDR3-1000 interface.

Technical Context

The R9A06G032NGBG#AC1 implements a heterogeneous dual-CPU architecture: two 500 MHz Arm Cortex-A7 cores with L1/L2 cache and MMU for Linux-capable host processing, plus a dedicated 125 MHz Cortex-M3 core for real-time R-IN Engine tasks including hardware-accelerated RTOS, Ethernet offload, and deterministic protocol stack execution.

Its networking subsystem integrates three concurrent real-time Ethernet engines: the A5PSW switch (5 Gbit ports, IEEE 1588, VLAN, PRP/HSR option), independent GMACs (2× 10/100/1000 Mbps with PPS output and jumbo frame support), and protocol-specific slave controllers (EtherCAT v12, SercosIII) - all sharing memory-mapped access to 6 MB on-chip ECC SRAM and coordinated via mailbox/semaphore inter-core synchronization.

Key Specifications

Pinout & Package

Package: 400-pin LFBGA (17 mm × 17 mm, 0.8 mm pitch), RoHS-compliant, lead-free, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar industrial communication SoC applications.

Compared with R9A06G032VGBG and R9A06G033EGBA, R9A06G032NGBG#AC1 uniquely delivers PRP/HSR redundancy, dual GMACs, and full 6 MB ECC SRAM in the 400LFBGA package - essential for certified fault-tolerant industrial gateways requiring IEC 62439-3 compliance.

Availability

R9A06G032NGBG#AC1 is available at Aetrix Electronics and suitable for industrial Ethernet gateways, multi-protocol PLC controllers, and redundant fieldbus masters requiring stable component supply, long-term lifecycle support, and traceable sourcing for safety-critical deployments.

Supply support for R9A06G032NGBG#AC1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.

The RZ/N1 series - including R9A06G032NGBG#AC1 - was designed specifically for industrial Ethernet convergence, integrating real-time protocol accelerators, redundancy engines, and safety-certifiable memory to replace FPGA-based gateways with single-chip solutions.

FAQ

What is the maximum operating frequency of the Arm Cortex-A7 cores in the R9A06G032NGBG#AC1?

The R9A06G032NGBG#AC1 features dual Arm Cortex-A7 cores operating at up to 500 MHz. This frequency is achievable under specified voltage (1.15 V ± 0.05 V) and temperature (−40°C to +110°C junction) conditions, with dynamic frequency scaling supported for thermal and power management. The R9A06G032NGBG#AC1 datasheet confirms this rating in Section 1.1 and Table 1.1.

Does the R9A06G032NGBG#AC1 support PRP and HSR simultaneously?

No, the R9A06G032NGBG#AC1 does not support PRP and HSR simultaneously. According to Section 1.3 Note 5 of the datasheet, HW-RTOS and HSR are mutually exclusive, and Note 6 states that SERCOSIII, ETHERCAT, and HSR functions cannot operate concurrently. PRP is available as an option in the R9A06G032NGBG#AC1 variant, but HSR activation disables PRP functionality.

How much on-chip SRAM does the R9A06G032NGBG#AC1 provide, and is ECC enabled by default?

The R9A06G032NGBG#AC1 integrates 6 MB of on-chip extended SRAM with SEC-DED (Single Error Correction, Double Error Detection) ECC. ECC is hardware-implemented and configurable via software - it can be enabled or disabled per memory region. The full 6 MB capacity is accessible only in the RZ/N1D group (which includes R9A06G032NGBG#AC1), as confirmed in Table 1.1 and Section 1.3.

What Ethernet protocols does the R9A06G032NGBG#AC1 support natively in hardware?

The R9A06G032NGBG#AC1 supports EtherCAT Slave (3 ports), SercosIII Slave (2 ports), PRP (IEC 62439-3), HSR (IEC 62439-3), and standard IEEE 802.3 10/100/1000 Mbps via its A5PSW and dual GMACs. All protocol acceleration - including distributed clocks, telegram processing, and redundancy frame handling - is implemented in dedicated hardware blocks, not software-only stacks.

What is the package type and pin count of the R9A06G032NGBG#AC1?

The R9A06G032NGBG#AC1 uses a 400-pin LFBGA package measuring 17 mm × 17 mm with 0.8 mm ball pitch. This is explicitly listed in Table 1.3 (List of Products) and Figure 1.4 (Pinout BGA-400) of the R01DS0323EJ0130 datasheet. It is distinct from the 324LFBGA and 196LFBGA variants used in other RZ/N1 family members.