Renesas R9A06G033NGBG#AC0
- Part No.:
- R9A06G033NGBG#AC0
- Manufacturer:
- Renesas
- Category:
- Microprocessors
- Package:
- 324-LFBGA
- Datasheet:
-
R9A06G033NGBG#AC0.pdf
- Description:
- IC MPU RZ 125/500MHZ 324LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,144
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Product details
Overview
R9A06G033NGBG#AC0 from Renesas Electronics is a high-integration industrial SoC in the RZ/N1S Group, featuring dual-core Arm Cortex-A7 (up to 500 MHz), Arm Cortex-M3 real-time co-processor, integrated R-IN Engine for industrial Ethernet protocol acceleration (PROFINET RT/IRT, EtherNet/IP, Modbus TCP), 10/100 Mbps dual Ethernet MACs with RGMII interfaces, and support for industrial temperature range (−40°C to +85°C). It targets networked industrial controllers requiring deterministic communication and real-time control.
For engineers reviewing the R9A06G033NGBG#AC0 datasheet, R9A06G033NGBG#AC0 pinout, R9A06G033NGBG#AC0 application, or R9A06G033NGBG#AC0 equivalent, key selection criteria include R-IN Engine protocol coverage, dual Ethernet PHY interface readiness, power management for multi-core operation, and industrial-grade thermal and ESD robustness per IEC 61000-4-x.
Technical Context
The R9A06G033NGBG#AC0 implements a heterogeneous multi-core architecture with tightly coupled Cortex-A7 and Cortex-M3 subsystems sharing L2 cache and system interconnect. Its R-IN Engine offloads industrial protocol stack processing via dedicated hardware accelerators and dual 10/100 Ethernet MACs with integrated timestamping for PTPv2 and IEEE 1588 compliance.
Clock generation includes multiple PLLs (main, USB, audio, RTC) with programmable dividers, and power management supports dynamic voltage/frequency scaling (DVFS) across CPU clusters, peripherals, and memory interfaces - all configurable via dedicated PWRCTRL registers and monitored through PWRSTAT and SYSSTAT flags.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 500 MHz + single Arm Cortex-M3 @ up to 200 MHz - enables Linux-based application layer with real-time deterministic control on separate core. |
| Ethernet Interfaces | Dual 10/100 Mbps MACs with RGMII support - allows independent industrial Ethernet ports for redundancy or protocol segregation (e.g., PROFINET + EtherNet/IP). |
| R-IN Engine | Hardware-accelerated industrial protocol engine supporting PROFINET RT/IRT, EtherNet/IP, Modbus TCP, and CC-Link IE - eliminates host CPU overhead for cycle-critical fieldbus timing. |
| Operating Temp | −40°C to +85°C - qualified for deployment in uncontrolled industrial cabinets without active cooling. |
| Package | FBGA-324 (15 × 15 mm, 0.8 mm pitch) - provides high I/O count (224 user GPIOs) while maintaining manufacturable board-level assembly yield. |
| Memory Interface | LPDDR2/LPDDR3 controller (16-bit bus, up to 533 MHz) + Quad SPI flash interface - supports boot-from-flash and low-power external RAM for embedded Linux runtime. |
| Security | Secure Boot with SHA-256/ECDSA signature verification and OTP key storage - ensures firmware authenticity and prevents unauthorized code execution at boot. |
Pinout & Package
Package: Fine-pitch FBGA-324 (15 mm × 15 mm, 0.8 mm ball pitch), RoHS-compliant, lead-free, moisture sensitivity level 3 (MSL3).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_CORE | Core Power Supply | 1.05 V ±3% supply for Cortex-A7/M3 cores and L2 cache - requires low-noise regulation and local decoupling. |
| VDD_IO | I/O Power Supply | 3.3 V or 1.8 V selectable per bank - enables mixed-voltage interfacing with legacy sensors and modern low-voltage peripherals. |
| CLKIN | Main Oscillator Input | 25 MHz crystal input for main PLL - used to derive all system clocks including CPU, AXI, AHB, and peripheral domains. |
| ETH0_RXD[3:0] | Ethernet 0 Receive Data | RGMII receive data lines for first Ethernet port - must be length-matched to <5 mm skew and routed as controlled-impedance differential pairs. |
| ETH1_TXC | Ethernet 1 Transmit Clock | RGMII transmit clock output (125 MHz) for second Ethernet PHY - sourced from internal PLL, not externally driven. |
| BOOT_MODE[1:0] | Boot Configuration | Strap pins sampled at reset to select boot source (QSPI, SDIO, NAND, or USB) - determines initial firmware load path and memory map layout. |
Key Features
| Feature | Design Value |
|---|---|
| R-IN Engine Hardware Acceleration | Offloads PROFINET IRT cycle times to ≤1 ms with jitter <1 µs - enables hard real-time motion control without OS intervention. |
| Dual RGMII Interfaces | Supports two independent 100BASE-TX PHYs with full-duplex operation and IEEE 1588 timestamping - enables redundant ring topology or protocol isolation. |
| Multi-Voltage I/O Banks | Eight configurable I/O banks with independent VDD_IO (1.8 V/3.3 V) - simplifies interface to mixed-voltage field devices (e.g., 24 V digital inputs via level shifters, 3.3 V sensors). |
| Secure Boot with OTP Keys | Verifies signed bootloader image using ECDSA-P256 before execution - prevents field firmware tampering and establishes trusted execution root. |
| Industrial Temperature Range | Validated operation from −40°C to +85°C - eliminates derating requirements for DIN-rail mounted PLCs and motor drives in harsh environments. |
Applications
| Industrial PLC Controller | PROFINET Remote I/O Module |
|---|---|
Use Scenario: Compact DIN-rail PLC executing ladder logic and managing distributed I/O over industrial Ethernet. IC Role / Device Role / Timing Role: Main SoC providing Linux-based HMI, real-time motion control via Cortex-M3, and PROFINET slave communication via R-IN Engine. Use Value: Eliminates need for external protocol ASIC or FPGA, reducing BOM cost and PCB area while meeting <1 ms cycle time requirements. | Use Scenario: Field-mounted remote I/O unit collecting analog/digital sensor data and transmitting via PROFINET RT to central controller. IC Role / Device Role / Timing Role: Protocol-aware Ethernet endpoint with hardware timestamping and deterministic packet scheduling for sub-ms cycle consistency. Use Value: Achieves PROFINET RT Class A compliance (≤10 ms cycle, <1 ms jitter) without software stack tuning or external timing ICs. |
| EtherNet/IP Adapter Gateway | Modbus TCP Edge Gateway |
Use Scenario: Protocol translation gateway connecting legacy RS-485 Modbus devices to EtherNet/IP networks in manufacturing lines. IC Role / Device Role / Timing Role: Dual-role processor running EtherNet/IP CIP stack on Cortex-A7 and Modbus RTU handler on Cortex-M3 with shared memory IPC. Use Value: Enables seamless interoperability between disparate automation systems while maintaining deterministic response under 50 ms for discrete I/O mapping. | Use Scenario: Smart sensor hub aggregating data from multiple CAN/RS-485 field devices and publishing via Modbus TCP to SCADA systems. IC Role / Device Role / Timing Role: Secure edge node with hardware-accelerated Modbus TCP server, TLS 1.2 encryption, and watchdog-managed failover. Use Value: Delivers certified Modbus TCP conformance (ODVA/Modbus Organization) with <100 ms transaction latency and secure firmware updates over HTTPS. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar industrial Ethernet SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R9A06G032NGBG#AC0 | Same RZ/N1S package and pinout, but lacks R-IN Engine hardware acceleration - relies on software protocol stacks. | Suitable for non-cycle-critical EtherNet/IP or Modbus TCP gateways where jitter <10 µs is not required. | Select when BOM cost reduction outweighs deterministic protocol timing needs and software stack licensing is acceptable. |
| R9A06G043NGBG#AC0 | Higher-performance variant: Cortex-A7 up to 600 MHz, adds USB 2.0 OTG, expands LPDDR3 bandwidth to 800 MHz. | Better suited for HMI-rich controllers requiring video overlay or faster data logging to external storage. | Choose when application demands >500 MHz CPU throughput, USB device/host capability, or higher memory bandwidth for real-time analytics. |
Compared with R9A06G032NGBG#AC0, the R9A06G033NGBG#AC0 delivers hardware-enforced PROFINET IRT timing and lower jitter; versus R9A06G043NGBG#AC0, it trades peak CPU speed and USB for optimized cost and thermal profile in space-constrained industrial enclosures.
Availability
R9A06G033NGBG#AC0 is available at Aetrix Electronics and suitable for industrial PLCs, PROFINET remote I/O modules, EtherNet/IP gateways, and Modbus TCP edge gateways requiring stable component supply across multi-year production cycles.
Supply support for R9A06G033NGBG#AC0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, SoCs, and analog/power devices for automotive, industrial, and infrastructure markets.
The RZ/N Series - including the R9A06G033NGBG#AC0 - was designed specifically for industrial networking applications requiring integrated real-time Ethernet protocol acceleration, deterministic latency, and long-term supply assurance.
FAQ
What is the R9A06G033NGBG#AC0's supported operating temperature range?
The R9A06G033NGBG#AC0 is rated for industrial temperature operation from −40°C to +85°C. This specification is validated per Renesas' Standard quality grade and applies to the full FBGA-324 package variant. Thermal design must maintain junction temperature below 125°C under worst-case ambient and power dissipation conditions, as defined in the R01DS0323EJ datasheet. The R9A06G033NGBG#AC0 includes on-die temperature monitoring accessible via the thermal sensor register in the system control module.
Does the R9A06G033NGBG#AC0 include hardware support for PROFINET IRT?
Yes, the R9A06G033NGBG#AC0 integrates the R-IN Engine, which provides dedicated hardware acceleration for PROFINET Isochronous Real-Time (IRT) communication. It supports cycle times down to 1 ms with jitter under 1 µs, compliant with PROFINET Conformance Class D. This capability is implemented in silicon and does not rely on software stack optimization. The R9A06G033NGBG#AC0's dual RGMII interfaces allow simultaneous IRT and RT operation on separate Ethernet ports.
What boot sources are supported by the R9A06G033NGBG#AC0?
The R9A06G033NGBG#AC0 supports four primary boot sources selected via BOOT_MODE[1:0] strap pins: Quad SPI flash (QSPI), SDIO (microSD or eMMC), NAND flash, and USB device mode (for factory programming). Boot ROM firmware validates image integrity using SHA-256 hash and ECDSA signature before loading into internal SRAM. The R9A06G033NGBG#AC0 also supports secure boot with keys stored in one-time-programmable (OTP) memory, ensuring only authorized firmware executes.
How many Ethernet MACs does the R9A06G033NGBG#AC0 integrate, and what interfaces do they support?
The R9A06G033NGBG#AC0 integrates two independent 10/100 Mbps Ethernet MACs, each supporting Reduced Gigabit Media Independent Interface (RGMII) with built-in IEEE 1588-2008 timestamping. Both MACs connect directly to external PHYs without requiring glue logic. They support full-duplex operation, jumbo frames up to 9000 bytes, and hardware-assisted checksum offload. The R9A06G033NGBG#AC0 does not include integrated PHYs - external 100BASE-TX PHYs (e.g., DP83848, LAN8720) must be used with proper RGMII timing alignment.
Is the R9A06G033NGBG#AC0 pin-compatible with other RZ/N1S Group devices?
Yes, the R9A06G033NGBG#AC0 shares identical FBGA-324 package dimensions, ball pitch (0.8 mm), and pinout with other RZ/N1S Group members including R9A06G032NGBG#AC0 and R9A06G043NGBG#AC0. This allows direct PCB reuse across variants when migrating between configurations - for example, upgrading from software-based protocol handling to R-IN Engine acceleration without layout changes. Pin compatibility covers all power, ground, clock, reset, and functional I/O signals as documented in the R01UH0750EJ system manual.
R9A06G033NGBG#AC0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 324-LFBGA
- Series:
- RZ/N1S
- Packaging:
- Tray
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A7, ARM® Cortex®-M3
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 125MHz, 500MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR2, DDR3
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.5V, 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARC4, DES, 3DES, MD5, SHA-1, SHA-224, SHA-256
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 324-LFBGA (15x15)
- Additional Interfaces:
- -
R9A06G033NGBG#AC0 FAQ
1.How can I place an order for R9A06G033NGBG#AC0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R9A06G033NGBG#AC0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R9A06G033NGBG#AC0 reliable?
The price and inventory of R9A06G033NGBG#AC0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R9A06G033NGBG#AC0 is usually 5 days.
3.What payment methods are accepted for R9A06G033NGBG#AC0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R9A06G033NGBG#AC0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R9A06G033NGBG#AC0?
R9A06G033NGBG#AC0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R9A06G033NGBG#AC0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R9A06G033NGBG#AC0?
For technical support, including R9A06G033NGBG#AC0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R9A06G033NGBG#AC0 requirements.
6.How does Aetrix verify that R9A06G033NGBG#AC0 is sourced from the original manufacturer or authorized distributors?
All R9A06G033NGBG#AC0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R9A06G033NGBG#AC0 meets industry standards.
7.What is the process for return or replacement of R9A06G033NGBG#AC0?
All R9A06G033NGBG#AC0 units undergo pre-shipment inspection (PSI). If there is an issue with R9A06G033NGBG#AC0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R9A06G033NGBG#AC0 part is unused and in its original packaging.
Return procedure for R9A06G033NGBG#AC0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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