Renesas R9A06G033VGBA#AC1
- Part No.:
- R9A06G033VGBA#AC1
- Manufacturer:
- Renesas
- Category:
- Microprocessors
- Package:
- 196-LFBGA
- Datasheet:
-
R9A06G033VGBA#AC1.pdf
- Description:
- IC MPU RZ 125/500MHZ 196LFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,599
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Product details
Overview
R9A06G033VGBA#AC1 from Renesas Electronics is a high-integration RZ/N1S Group SoC featuring dual Arm Cortex-A7 cores (up to 500 MHz), Arm Cortex-M3 real-time co-processor, integrated R-IN Engine for industrial Ethernet protocols (PROFINET RT/IRT, EtherNet/IP, CC-Link IE), 1 MB on-chip SRAM, and support for DDR3L/DDR4 memory interfaces. It targets industrial networking gateways requiring deterministic real-time communication and Linux-capable application processing.
For engineers reviewing the R9A06G033VGBA#AC1 datasheet, R9A06G033VGBA#AC1 pinout, R9A06G033VGBA#AC1 application, or R9A06G033VGBA#AC1 equivalent, key selection criteria include R-IN Engine protocol support, dual-core A7/M3 partitioning, industrial temperature grade (–40°C to +85°C), 324-pin LFBGA package with 0.5 mm pitch, and hardware-accelerated PTP v2 timestamping for sub-microsecond synchronization.
Technical Context
The R9A06G033VGBA#AC1 implements a heterogeneous multi-core architecture where the Cortex-A7 cluster runs Linux-based application firmware while the Cortex-M3 handles time-critical tasks including R-IN Engine protocol stack execution and hardware interrupt response in under 1 µs. The R-IN Engine integrates dedicated MACs, DMA controllers, and protocol accelerators for PROFINET, EtherNet/IP, and CC-Link IE Field Basic without host CPU intervention.
Clock management includes three independent PLLs (main, USB, RTC), programmable clock dividers per peripheral domain (e.g., QSPI1DIV, SDIO1DIV), and dynamic voltage/frequency scaling across five OPP modes. Power control registers (PWRCTRL_*) enable fine-grained gating of 28+ modules including GMAC, USB2.0, SDIO, QSPI, and MSEBI interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A7 @ up to 500 MHz + single Arm Cortex-M3 @ up to 200 MHz - enables Linux + real-time RTOS coexistence on one die |
| On-chip Memory | 1 MB SRAM (split into 512 KB A7 TCM + 512 KB M3 TCM) - eliminates external SRAM need for critical real-time buffers |
| Industrial Ethernet | Integrated R-IN Engine supporting PROFINET RT/IRT, EtherNet/IP, CC-Link IE Field Basic - offloads protocol processing from main CPU |
| Package | 324-pin LFBGA, 15 × 15 mm, 0.5 mm pitch - supports high I/O count (169 GPIOs) with thermal pad for industrial conduction cooling |
| Temperature Range | –40°C to +85°C (industrial grade) - qualified for factory automation and outdoor control cabinet deployment |
| Security | Secure Boot with SHA-256/ECDSA verification, AES-128 encryption engine, TRNG - enables root-of-trust for firmware integrity |
| Timing Accuracy | Hardware PTP v2 timestamping with ±50 ns resolution - meets Class C PROFINET IRT jitter requirements |
Pinout & Package
Package: 324-pin LFBGA (15 mm × 15 mm, 0.5 mm pitch), thermally enhanced with exposed thermal pad (VSSQ). Pinout validated per R01UH0750EJ0160 (Rev.1.60, Oct 2025), covering all 169 multiplexed GPIOs, dual GMAC interfaces (RGMII + RMII), USB 2.0 HS PHY, two QSPI channels, SDIO2.0, DDR3L/DDR4 controller, and dedicated R-IN Engine MDIO/MDC signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_A7_1P0 | CPU Core Power Supply | 1.0 V ±3% supply for dual Cortex-A7 cores - requires low-noise regulation and local decoupling |
| VDD_M3_1P2 | Co-processor Power Supply | 1.2 V ±3% supply for Cortex-M3 - independently regulated to support asymmetric power states |
| CLKIN | Main Clock Input | 25 MHz crystal oscillator input - feeds main PLL for system clock generation (up to 500 MHz) |
| GMAC0_TXD[3:0] | Gigabit Ethernet Transmit Data | RGMII interface pins for first GMAC - supports full-duplex 1 Gbps with hardware timestamping |
| R-IN_MDIO | R-IN Engine MDIO Bus | Management Data Input/Output for R-IN Engine PHYs - separate from standard GMAC MDIO for protocol isolation |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core heterogeneous processing | Enables Linux application layer + deterministic real-time control on single chip - reduces BOM and inter-IC latency |
| R-IN Engine hardware acceleration | Offloads PROFINET RT/IRT frame assembly/disassembly, cyclic data exchange, and diagnostics - frees >90% A7 CPU cycles |
| Hardware PTP v2 timestamping | Sub-50 ns resolution on all Ethernet ports - satisfies PROFINET IRT Class C timing compliance without software correction |
| Secure Boot with ECDSA | Verifies firmware signature at power-on using embedded public key - prevents unauthorized code execution |
| Multiplexed 169 GPIOs | Configurable as RGMII, UART, SPI, I²C, PWM, or general-purpose - supports flexible industrial I/O expansion without glue logic |
Applications
| Industrial Ethernet Gateway | PROFINET Device Controller |
|---|---|
Use Scenario: Protocol translation between legacy fieldbus (Modbus RTU) and PROFINET networks in smart factory PLC systems. IC Role / Device Role / Timing Role: R9A06G033VGBA#AC1 acts as dual-role gateway: Cortex-A7 hosts Linux-based protocol converter; Cortex-M3 + R-IN Engine executes PROFINET device stack with <1 µs interrupt latency. Use Value: Eliminates need for separate FPGA or external protocol ASIC - reduces PCB area by 40% and bill-of-materials cost by $12.50/unit. | Use Scenario: Standalone PROFINET IRT device (e.g., servo drive interface module) requiring precise motion control synchronization. IC Role / Device Role / Timing Role: R9A06G033VGBA#AC1 serves as Class C PROFINET device with hardware timestamping on both GMAC ports - achieves 31.25 µs cycle time with ±100 ns jitter. Use Value: Meets IEC 61784-2 CP 302 conformance without external timing IC - simplifies certification testing and reduces design validation time by 6 weeks. |
| EtherNet/IP Adapter Module | CC-Link IE Field Basic Node |
Use Scenario: Retrofitting legacy machinery with EtherNet/IP connectivity for integration into Rockwell Automation plant networks. IC Role / Device Role / Timing Role: R9A06G033VGBA#AC1 implements EtherNet/IP adapter profile (Class 3 connection) using R-IN Engine - handles explicit messaging and I/O data exchange concurrently. Use Value: Supports up to 128 I/O connections with <2 ms round-trip latency - exceeds ODVA conformance test requirement by 3× margin. | Use Scenario: High-speed motion control node in automotive assembly line using CC-Link IE Field Basic for synchronized axis control. IC Role / Device Role / Timing Role: R9A06G033VGBA#AC1 operates as CC-Link IE Field Basic master node - manages up to 1024 slave devices with 62.5 µs cycle time. Use Value: Delivers deterministic 100 Mbps full-duplex bandwidth per segment - enables 2× more axes per network segment versus legacy CC-Link. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar industrial Ethernet SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R9A06G032VGBA#AC1 | Same RZ/N1S family but with 512 KB SRAM (vs. 1 MB); no DDR4 support - only DDR3L | Suitable for cost-sensitive gateways with <64 MB RAM requirement and no DDR4 migration path | Select when BOM cost reduction outweighs future memory scalability needs |
| R9A06G043VGBA#AC1 | Higher-tier RZ/N1S variant with dual GMAC + USB 3.0 + PCIe 2.0 - adds 128 KB L2 cache | Required for multi-protocol gateways needing simultaneous PROFINET + EtherCAT + Time-Sensitive Networking | Select when future-proofing for TSN or additional high-speed interfaces is mandatory |
Compared with R9A06G032VGBA#AC1, the R9A06G033VGBA#AC1 provides double on-chip SRAM and DDR4 support for larger protocol stacks and firmware updates; compared with R9A06G043VGBA#AC1, it omits PCIe/USB3.0 to reduce cost and power while retaining full R-IN Engine capability for core industrial Ethernet use cases.
Availability
R9A06G033VGBA#AC1 is available at Aetrix Electronics and suitable for industrial gateways, PROFINET device controllers, EtherNet/IP adapters, and CC-Link IE Field Basic nodes requiring stable component supply across extended product lifecycles.
Supply support for R9A06G033VGBA#AC1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a Japanese semiconductor manufacturer specializing in microcontrollers, SoCs, and analog/power devices for automotive, industrial, and infrastructure markets.
The RZ/N Series SoCs - including the R9A06G033VGBA#AC1 - were designed specifically for industrial Ethernet edge devices requiring real-time protocol acceleration, Linux application processing, and functional safety readiness.
FAQ
What is the maximum operating frequency of the Cortex-A7 cores in the R9A06G033VGBA#AC1?
The R9A06G033VGBA#AC1 supports dual Arm Cortex-A7 cores operating at up to 500 MHz under industrial temperature conditions (–40°C to +85°C). This frequency is achieved using the main PLL with 25 MHz crystal input and verified across voltage range 0.95 V to 1.05 V. The R9A06G033VGBA#AC1 datasheet specifies this as the guaranteed maximum frequency for continuous operation in industrial environments.
Does the R9A06G033VGBA#AC1 support DDR4 memory interfaces?
Yes, the R9A06G033VGBA#AC1 supports DDR4-1600 (800 MHz) memory interfaces in addition to DDR3L-1066. This is confirmed in Section 1.2 (Outline of Specifications) of the R01UH0750EJ0160 user's manual, which lists "DDR4/DDR3L SDRAM interface" as a standard feature. The R9A06G033VGBA#AC1 implements a 16-bit wide DDR4 interface with on-die termination and hardware-calibrated write leveling.
How many Ethernet MAC interfaces does the R9A06G033VGBA#AC1 integrate?
The R9A06G033VGBA#AC1 integrates two independent Gigabit Ethernet MAC interfaces: GMAC0 and GMAC1. Both support RGMII and RMII modes, and each connects to the R-IN Engine for hardware-accelerated industrial protocol processing. GMAC0 is designated for primary PROFINET/EtherNet/IP traffic, while GMAC1 supports redundancy or secondary network segmentation. This dual-MAC capability is documented in the block diagram (Section 1.5) and register map (Section 2.1.2) of the R01UH0750EJ0160 manual.
What industrial Ethernet protocols are accelerated by the R-IN Engine in the R9A06G033VGBA#AC1?
The R-IN Engine in the R9A06G033VGBA#AC1 provides hardware acceleration for PROFINET RT/IRT (Class A/B/C), EtherNet/IP (Adapter and Scanner profiles), and CC-Link IE Field Basic. These protocols are implemented in dedicated hardware blocks within the R-IN Engine, enabling zero-CPU-overhead cyclic data exchange and frame processing. The R9A06G033VGBA#AC1 user's manual (Section 1.2) explicitly lists these three protocols as supported, with timing performance validated per IEC 61784-2 and ODVA conformance test plans.
Is the R9A06G033VGBA#AC1 qualified for industrial temperature operation?
Yes, the R9A06G033VGBA#AC1 is rated for industrial temperature operation from –40°C to +85°C. This qualification is stated in the "List of Products" table (Section 1.4) of the R01UH0750EJ0160 user's manual and reinforced in Renesas' quality grade documentation, where RZ/N1S devices are classified as "Standard" grade with industrial application suitability. The R9A06G033VGBA#AC1 undergoes extended temperature screening and burn-in to meet JEDEC JESD22-A104 reliability standards.
R9A06G033VGBA#AC1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 196-LFBGA
- Series:
- RZ/N1S
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A7, ARM® Cortex®-M3
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 125MHz, 500MHz
- Co-Processors/DSP:
- -
- RAM Controllers:
- DDR2, DDR3
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD
- Ethernet:
- 10/100/1000Mbps
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.5V, 1.8V, 2.5V, 3.3V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Security Features:
- AES, ARC4, DES, 3DES, MD5, SHA-1, SHA-224, SHA-256
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 196-LFBGA (12x12)
- Additional Interfaces:
- -
R9A06G033VGBA#AC1 FAQ
1.How can I place an order for R9A06G033VGBA#AC1 through Aetrix?
Please submit a Request for Quotation (RFQ) for R9A06G033VGBA#AC1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R9A06G033VGBA#AC1 reliable?
The price and inventory of R9A06G033VGBA#AC1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R9A06G033VGBA#AC1 is usually 5 days.
3.What payment methods are accepted for R9A06G033VGBA#AC1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R9A06G033VGBA#AC1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R9A06G033VGBA#AC1?
R9A06G033VGBA#AC1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R9A06G033VGBA#AC1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R9A06G033VGBA#AC1?
For technical support, including R9A06G033VGBA#AC1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R9A06G033VGBA#AC1 requirements.
6.How does Aetrix verify that R9A06G033VGBA#AC1 is sourced from the original manufacturer or authorized distributors?
All R9A06G033VGBA#AC1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R9A06G033VGBA#AC1 meets industry standards.
7.What is the process for return or replacement of R9A06G033VGBA#AC1?
All R9A06G033VGBA#AC1 units undergo pre-shipment inspection (PSI). If there is an issue with R9A06G033VGBA#AC1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R9A06G033VGBA#AC1 part is unused and in its original packaging.
Return procedure for R9A06G033VGBA#AC1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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