Renesas RAA230407GNP#HA0
- Part No.:
- RAA230407GNP#HA0
- Manufacturer:
- Renesas
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 32-VQFN
- Datasheet:
-
RAA230407GNP#HA0.pdf
- Description:
- IC REG QD BUCK/LNR SYNC 32VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,656
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
RAA230407GNP#HA0 from Renesas Electronics is a 3-channel synchronous step-down switching regulator with integrated power MOSFETs and 1-channel LDO, delivering preset 3.0 V (ch1), 3.3 V (ch2), adjustable (ch3), and 1.2 V (ch4) outputs. It supports 2.5–5.5 V input, delivers up to 1500 mA per buck channel, and integrates digital soft-start, thermal shutdown (≥150°C), and power-good (PG1) for ch1.
For engineers reviewing the RAA230407GNP#HA0 datasheet, RAA230407GNP#HA0 pinout, RAA230407GNP#HA0 application, or RAA230407GNP#HA0 equivalent, this device serves as a compact, multi-rail PMIC for FPGA I/O banks, microcontroller core/peripheral supplies, and industrial sensor nodes requiring independent channel control, low-power mode (SAVE pin), and robust short-circuit protection with SCP pin timing.
Technical Context
The RAA230407GNP#HA0 implements current-mode PWM control across all three buck regulators (ch1, ch3, ch4), each with integrated high- and low-side MOSFETs (Ron-p/n ≈ 0.4–0.6 Ω), internal phase compensation, and selectable 1.3–2 MHz switching frequency via RT resistor. Ch2 is a standalone LDO with foldback overcurrent protection and 0.5 V dropout at 20 mA.
It features independent ON/OFF control per channel via SHDNB0–SHDNB4 pins, a shared SCP pin enabling timer-latch short-circuit and thermal shutdown (both triggering at SCP = 0.9 V), and dual-mode ch4 output selection (CTL4 = H → 1.2 V fixed; CTL4 = L → external resistor adjustable). The IC operates in normal or low-power mode (15% fOSC) controlled by SAVE pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5 V to 5.5 V - Supports single Li-ion or USB-powered systems without pre-regulation. |
| Buck Output Channels | 3 × synchronous step-down (ch1/ch3/ch4) - ch1 preset 3.0 V @ 500 mA; ch3/ch4 adjustable or preset 1.2 V @ 1500 mA each. |
| LDO Output Channel | 1 × ch2 @ 3.3 V / 100 mA - Fixed output with 0.5 V dropout, foldback current limiting, and 1% accuracy. |
| Switching Frequency | 1.3 MHz to 2 MHz (RT-programmable) - Enables compact 2.2–4.7 µH inductors and reduces EMI in noise-sensitive applications. |
| Protection Features | Timer-latch thermal shutdown (≥150°C), SCP-triggered latch-off, UVLO (1.9–2.3 V start), and digital soft-start - Ensures safe startup and fault containment without external supervision. |
| Control Interface | Independent SHDNB0–SHDNB4 logic inputs + SAVE/CTL4 pins - Enables precise sequencing, dynamic rail enable/disable, and low-power mode entry without firmware. |
| Package | 32-pin VQFN (5 mm × 5 mm, 0.5 mm pitch, exposed thermal pad) - Optimized for thermal performance in space-constrained PCB layouts. |
Pinout & Package
RAA230407GNP#HA0 is housed in a 32-pin VQFN package (5 mm × 5 mm, 0.5 mm pitch) with an exposed thermal pad for enhanced heat dissipation. Pin numbering follows standard top-view layout with pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VPIN1, VPIN2, VPIN3, VPIN4 | Power input for ch1–ch4 | Direct connection to respective input rails; VPIN2 powers LDO only; others feed buck stages. |
| LOUT1, LOUT3, LOUT4 | Buck inductor connection | High-current switch node outputs; require low-ESR ceramic capacitors and proper layout for stability. |
| OUT2 | LDO output | Regulated 3.3 V supply; requires ≥2.2 µF ceramic output capacitor for stability. |
| SHDNB0–SHDNB4 | Channel enable/disable control | Active-high logic; internal 400 kΩ pull-down ensures default OFF state if unconnected. |
| CTL4 | Ch4 output mode select | H → 1.2 V fixed (internal resistor); L → adjustable (external R1/R2 divider referenced to 0.8 V). |
| SCP | Short-circuit/thermal fault timer | Capacitor-connected pin (0.1 µF typical) sets delay before latch-off; must tie to AGND if unused. |
| PG1 | Power-good indicator for ch1 | Open-drain output asserting low when ch1 output falls below 90% of set voltage; requires external pull-up. |
Key Features
| Feature | Design Value |
|---|---|
| Digital soft-start | Adjustable 2–4 ms startup time (via SS pin resistor) prevents inrush current and output overshoot during power-on. |
| Low-power mode | SAVE = H reduces ch1/ch3/ch4 switching frequency to 15% of nominal (e.g., ~300 kHz at 2 MHz base), cutting quiescent current to 0.7 mA. |
| Integrated discharge circuit | Active pull-down on LOUT1/LOUT3/LOUT4/OUT2 during shutdown - eliminates hold-up voltage and enables fast rail collapse for sequencing. |
| Thermal & short-circuit latch | Single SCP pin coordinates both protections; latches all outputs OFF until SHDNB0 toggle or AVDD reset - prevents repeated fault cycling. |
| Independent channel control | Five dedicated SHDNB pins allow arbitrary power-up/down sequencing (e.g., ch2 before ch1) without external logic or MCU intervention. |
Applications
| FPGA I/O Bank Supply | Microcontroller Core/Peripheral Rails |
|---|---|
|
Use Scenario: Powering multiple I/O banks on Xilinx Artix-7 or Intel Cyclone V FPGA with different voltage requirements (1.2 V, 1.8 V, 3.3 V). IC Role / Device Role / Timing Role: RAA230407GNP#HA0 provides ch4 (1.2 V), ch1 (3.0 V), ch2 (3.3 V), and ch3 (adjustable) as independent, sequenced rails. Use Value: Eliminates need for four discrete regulators; built-in soft-start and PG1 ensure reliable configuration loading and JTAG access. |
Use Scenario: Supplying ARM Cortex-M7 core (1.2 V), DDR3 interface (1.5 V), and analog peripherals (3.3 V) in industrial edge controller. IC Role / Device Role / Timing Role: RAA230407GNP#HA0 delivers ch4 (1.2 V), ch3 (1.5 V via external resistors), and ch2 (3.3 V) with independent enable timing. Use Value: Reduces BOM count and PCB area; low-power mode extends battery life during sleep cycles without sacrificing wake-up responsiveness. |
| Industrial Sensor Node | Automotive Body Control Module |
|
Use Scenario: Powering MEMS accelerometer, BLE SoC (3.3 V), and signal-conditioning op-amps (5 V derived externally) in wireless vibration monitor. IC Role / Device Role / Timing Role: RAA230407GNP#HA0 supplies ch2 (3.3 V BLE rail) and ch1 (3.0 V sensor bias) with independent shutdown for duty-cycled operation. Use Value: Standby current <2 µA (all channels off) enables >10-year battery life; SCP protection guards against sensor cable shorts. |
Use Scenario: Providing regulated supplies for LIN transceiver (5 V derived), CAN PHY (3.3 V), and microcontroller I/O (3.0 V) in door module. IC Role / Device Role / Timing Role: RAA230407GNP#HA0 configures ch2 (3.3 V CAN), ch1 (3.0 V I/O), and ch4 (1.2 V core) with UVLO and thermal latch for automotive-grade reliability. Use Value: –40°C to +85°C operation and 150°C thermal shutdown meet AEC-Q100 stress requirements; PG1 enables safe MCU reset on rail failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RGZR | 3 buck + 2 LDO; fixed 1.2/1.8/2.85 V outputs; no adjustable ch3/ch4; 2.25–6.5 V input; 2.25 MHz fSW | Lacks ch3/ch4 adjustability and SAVE low-power mode; higher input voltage range suits 12 V intermediate bus. | Choose TPS65023RGZR when fixed outputs and higher VIN tolerance outweigh need for programmability and ultra-low standby. |
| ISL9305IRTNZ-T | 2 buck + 2 LDO; ch1/ch2 adjustable; 2.7–5.5 V input; 3 MHz fSW; no SCP latch; thermal shutdown only | No shared fault coordination; lacks ch3/ch4 channel count and PG1 monitoring; smaller 4×4 mm QFN. | Choose ISL9305IRTNZ-T for space-constrained designs needing two adjustable bucks and two LDOs, but not full 4-rail sequencing or latch-type protection. |
Compared with TPS65023RGZR and ISL9305IRTNZ-T, RAA230407GNP#HA0 uniquely combines four independently controllable rails (3 buck + 1 LDO), adjustable ch3/ch4 outputs, integrated SCP/thermal latch coordination, and low-power mode - making it optimal for FPGA, multi-core MCU, and sensor hub designs demanding flexibility, safety, and efficiency.
Availability
RAA230407GNP#HA0 is available at Aetrix Electronics and suitable for FPGA power management, industrial sensor nodes, automotive body electronics, and embedded microcontroller systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for RAA230407GNP#HA0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power management, and connectivity solutions for automotive, industrial, and IoT markets.
The RAA23040x series is designed as highly integrated, multi-output PMICs targeting space- and power-constrained embedded systems requiring precise rail sequencing, robust fault protection, and minimal external components.
FAQ
What output voltages does the RAA230407GNP#HA0 provide?
The RAA230407GNP#HA0 delivers ch1 = 3.0 V (preset), ch2 = 3.3 V (LDO), ch3 = adjustable (external resistor), and ch4 = 1.2 V (preset). Ch4 output mode is selected by CTL4 pin: high for 1.2 V fixed, low for adjustable. All outputs are independently enabled via SHDNB pins, and ch1 includes a power-good (PG1) signal.
How is the switching frequency set on the RAA230407GNP#HA0?
The RAA230407GNP#HA0 switching frequency for ch1/ch3/ch4 is set by an external resistor on the RT pin, ranging from 1.3 MHz to 2 MHz. The approximate formula is fOSC[MHz] = –0.107 × RT[kΩ] + 3.05. For example, a 10 kΩ RT resistor yields ~2 MHz. Frequency accuracy is ±10% over voltage and temperature.
Does the RAA230407GNP#HA0 support power sequencing between channels?
Yes, the RAA230407GNP#HA0 supports precise power sequencing via five independent SHDNB pins (SHDNB0–SHDNB4). Each channel can be enabled/disabled in any order and timing - for example, asserting SHDNB2 before SHDNB1 ensures ch2 (3.3 V LDO) powers up prior to ch1 (3.0 V buck), critical for I/O voltage ordering in FPGAs and MCUs.
What protection features are integrated into the RAA230407GNP#HA0?
The RAA230407GNP#HA0 integrates timer-latch short-circuit protection (SCP), thermal shutdown (≥150°C), under-voltage lockout (UVLO: 1.9–2.3 V start), and digital soft-start. SCP and thermal faults share the same SCP pin and trigger coordinated latch-off of all outputs - requiring SHDNB0 toggle or AVDD reset to recover.
Can the RAA230407GNP#HA0 operate in low-power mode, and how is it activated?
Yes, the RAA230407GNP#HA0 enters low-power mode when the SAVE pin is driven high, reducing ch1/ch3/ch4 switching frequency to 15% of nominal (e.g., ~300 kHz at 2 MHz base) and lowering operating current to 0.7 mA. This mode is intended for light-load conditions (<100 mA per buck channel) and increases output ripple - design trade-offs must be verified.
RAA230407GNP#HA0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 32-VQFN
- Packaging:
- Tray
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (3), Linear (LDO) (1)
- Number of Outputs:
- 4
- Frequency - Switching:
- 1.3MHz ~ 2.2MHz
- Voltage/Current - Output 1:
- 3V, 500mA
- Voltage/Current - Output 2:
- 3V, 100mA
- Voltage/Current - Output 3:
- 0.9V ~ 4.95V, 1.5A
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-VQFN (5x5)
RAA230407GNP#HA0 FAQ
1.How can I place an order for RAA230407GNP#HA0 through Aetrix?
Please submit a Request for Quotation (RFQ) for RAA230407GNP#HA0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for RAA230407GNP#HA0 reliable?
The price and inventory of RAA230407GNP#HA0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for RAA230407GNP#HA0 is usually 5 days.
3.What payment methods are accepted for RAA230407GNP#HA0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for RAA230407GNP#HA0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for RAA230407GNP#HA0?
RAA230407GNP#HA0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your RAA230407GNP#HA0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for RAA230407GNP#HA0?
For technical support, including RAA230407GNP#HA0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your RAA230407GNP#HA0 requirements.
6.How does Aetrix verify that RAA230407GNP#HA0 is sourced from the original manufacturer or authorized distributors?
All RAA230407GNP#HA0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that RAA230407GNP#HA0 meets industry standards.
7.What is the process for return or replacement of RAA230407GNP#HA0?
All RAA230407GNP#HA0 units undergo pre-shipment inspection (PSI). If there is an issue with RAA230407GNP#HA0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The RAA230407GNP#HA0 part is unused and in its original packaging.
Return procedure for RAA230407GNP#HA0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
RAA230407GNP#HA0 Tags

-
TPS6521905RHBR
Texas Instruments

-
MIC3385YHL-TR
Microchip Technology

-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments

-
A4402KLPTR-T
Allegro MicroSystems

-
BD71847AMWV-E2
ROHM Semiconductor

-
ADP5040ACPZ-1-R7
Analog Devices Inc.

-
LT3048IDC#TRPBF
Analog Devices Inc.

-
ADP5037ACPZ-R7
Analog Devices Inc.

-
XRP7714ILB-F
MaxLinear, Inc.

-
LTC3260EDE#TRPBF
Analog Devices Inc.

-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
