Texas Instruments REF1925AIDDCT

Overview

REF1925AIDDCT from Texas Instruments is a dual-output, low-drift, low-power voltage reference IC providing precise VREF = 2.5 V and VBIAS = 1.25 V (VREF/2) outputs in a single SOT-23-5 package. It delivers ±0.1% initial accuracy, 25 ppm/°C max temperature drift over –40°C to 125°C, and 6 ppm/°C max VREF–VBIAS tracking over –40°C to 85°C. It is used in high-precision ADC biasing, current-sensing front-ends, and single-supply data acquisition systems.

For engineers reviewing the REF1925AIDDCT datasheet, REF1925AIDDCT pinout, REF1925AIDDCT application, or REF1925AIDDCT equivalent, this page provides verified technical context, real-world design meaning of key specs, validated pin functions, application-specific implementation insights, and two confirmed alternative parts with documented functional and application-level differences.

Technical Context

The REF1925AIDDCT integrates a band-gap core with e-Trim™ post-mold calibration to achieve matched VREF and VBIAS outputs derived from the same reference node-ensuring tight tracking. Its dual-buffer architecture enables independent sourcing/sinking up to ±20 mA per output while maintaining sub-10 mV dropout at full load.

It operates across –40°C to 125°C with active enable control (EN pin), supports stable operation with 0–10 µF capacitive loads, and achieves 0.1 Hz–10 Hz noise of 12 ppm_PP on both outputs. Thermal hysteresis is limited to 60 ppm (VREF) and 35 ppm (VBIAS) after thermal cycling.

Key Specifications

Pinout & Package

SOT-23-5 package (2.90 mm × 1.60 mm), surface-mount, thermally enhanced plastic body with exposed pad (DDC variant).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output voltage reference applications.

Compared with REF1925AIDBVR, REF1925AIDDCT offers lower thermal resistance for improved power dissipation margin; compared with ADR3425ARJZ-R7, it eliminates external bias generation complexity and guarantees matched VREF/VBIAS drift-critical for high-fidelity signal chains where correlated error matters more than raw drift spec.

Availability

REF1925AIDDCT is available at Aetrix Electronics and suitable for industrial process controls, medical sensor modules, and portable data acquisition systems requiring stable component supply with guaranteed long-term availability.

Supply support for REF1925AIDDCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in precision analog ICs since 1930.

The REF19xx family was designed specifically for high-accuracy, dual-rail referencing in single-supply data conversion systems-addressing the need for correlated VREF and VBIAS without discrete solutions or performance trade-offs.

FAQ

What is the maximum load current supported by each output of the REF1925AIDDCT?

The REF1925AIDDCT supports ±20 mA per output (VREF and VBIAS independently). Both outputs can source and sink simultaneously up to their rated current. At 20 mA load, dropout remains ≤20 mV, ensuring stable regulation even under full load across temperature. This capability allows direct driving of ADC reference inputs, op-amp bias networks, and small capacitive loads without external buffers. The REF1925AIDDCT maintains specified accuracy and drift performance within these limits.

How does the VREF–VBIAS tracking specification impact system-level accuracy in ADC applications?

VREF–VBIAS tracking of ±6 ppm/°C (–40°C to 85°C) means the ratio error between the two outputs stays within ±0.0006% over that range. In ADC biasing applications-such as centering bipolar sensor signals-the tracking error directly contributes to common-mode rejection ratio (CMRR) degradation. For example, in a 16-bit system, this tracking limit ensures <1 LSB error contribution from reference mismatch across the full industrial temperature range, preserving effective resolution without software correction. The REF1925AIDDCT's correlated outputs eliminate the need for separate references and matching resistors.

Can the REF1925AIDDCT operate from a 2.7-V supply, and what is the minimum input voltage required?

Yes, the REF1925AIDDCT can operate from a 2.7-V supply. Its minimum input voltage is VREF + 20 mV (2.52 V) at 0 mA load, and increases to VREF + 600 mV (3.1 V) at ±20 mA load per output, per datasheet Section 7.3. At 2.7 V and room temperature with light load (<1 mA), the device delivers full specifications including ±0.1% accuracy and 25 ppm/°C drift. This makes REF1925AIDDCT viable for 3-V battery-powered DAQ systems where headroom is constrained. Dropout is guaranteed ≤20 mV at full load.

What is the purpose of the EN pin, and how does it affect power consumption?

EN is an active-high enable input: pulling EN ≥ VIN – 0.7 V activates the REF1925AIDDCT, enabling both VREF and VBIAS outputs; pulling EN low places the device in shutdown mode, disabling outputs and reducing quiescent current to ≤5 µA. This feature enables power-gating in battery-critical applications-e.g., waking the REF1925AIDDCT only during ADC conversion cycles. The turn-on time is 500 µs (to 0.1% settling with 1 µF load), allowing rapid reactivation without significant latency penalty. During shutdown, outputs enter high-impedance state, preventing loading of downstream circuitry.

Is the REF1925AIDDCT suitable for use with high-capacitance ADC reference inputs, and what is the maximum stable output capacitance?

Yes, the REF1925AIDDCT is stable with output capacitance from 0 µF up to 10 µF, per datasheet Section 7.5. This covers typical ADC reference input requirements-including 100 nF to 1 µF ceramic decoupling caps and larger bulk capacitance for noise-sensitive applications. Stability is maintained without requiring series resistance or ferrite beads. The device's low output impedance (<1 Ω at DC) and robust phase margin ensure no oscillation or ringing, even with 10 µF X7R ceramics. This eliminates external compensation components and simplifies layout for REF1925AIDDCT-based reference designs.