Renesas RM24C128DS-LMAI-T

Overview

RM24C128DS-LMAI-T from Adesto Technologies is a 128Kbit non-volatile serial EEPROM IC using CBRAM® resistive memory technology, operating from 1.65V to 3.6V with I²C interface up to 1 MHz, 64-byte page size, and integrated 128-byte OTP security register. It serves as a low-energy, high-endurance data storage element in space-constrained embedded systems requiring secure configuration or calibration data retention.

For engineers reviewing the RM24C128DS-LMAI-T datasheet, RM24C128DS-LMAI-T pinout, RM24C128DS-LMAI-T application, or RM24C128DS-LMAI-T equivalent, key selection criteria include its 100,000 write cycles at full temperature range, 50 nJ byte-write energy, 3 ms page-write time, 40-year data retention at 125°C, and dual-access capability for both main EEPROM array and factory/user OTP registers via distinct I²C control codes (1010/1011).

Technical Context

The RM24C128DS-LMAI-T implements a slave-only I²C interface with SDA/SCL pins, three external device-select enable inputs (E0–E2), and hardware write-protect (WP) pin. Its internal architecture includes a 64-byte page buffer, address latch & counter, and resistive memory array organized as 128 Kbit (16,384 × 8), supporting random and sequential read modes with no read-cycle degradation.

It uses Adesto's proprietary CBRAM® technology-enabling true byte-level writes without read-modify-write overhead, eliminating endurance penalty across temperature, and delivering 4–6× faster page writes versus floating-gate EEPROMs. The OTP security register (128 bytes: 64 factory-programmed UID + 64 user-programmable) shares the same address pointer but uses separate I²C control code (1011) and masked 7-bit addressing.

Key Specifications

Pinout & Package

RM24C128DS-LMAI-T is packaged in an 8-lead SOIC (Small Outline Integrated Circuit) with standard JEDEC MS-012AC footprint, compatible with automated PCB assembly and reflow profiles.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT24C128C-SSHL-T and M95128-DFMN6TP, RM24C128DS-LMAI-T uniquely combines I²C compatibility, 100,000-cycle endurance across full temperature range, 50 nJ byte-write energy, and integrated OTP security - making it optimal for next-generation secure, low-power, thermally demanding embedded systems where interface consistency and long-term reliability are non-negotiable.

Availability

RM24C128DS-LMAI-T is available at Aetrix Electronics and suitable for smart metering, industrial PLCs, medical sensors, and automotive body control modules requiring stable component supply, long-lifecycle support, and guaranteed RoHS/halogen-free compliance.

Supply support for RM24C128DS-LMAI-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Adesto Technologies (acquired by Dialog Semiconductor in 2020, now part of Renesas Electronics) specialized in ultra-low-power, high-reliability non-volatile memory solutions for constrained embedded applications.

The RM24C128DS-LMAI-T belongs to Adesto's CBRAM®-based serial EEPROM product line, designed specifically for applications demanding superior write endurance, minimal energy per operation, and secure identity storage in thermally aggressive environments.

FAQ

What is the maximum I²C clock frequency supported by RM24C128DS-LMAI-T?

The RM24C128DS-LMAI-T supports I²C clock frequencies up to 1 MHz across its full operating voltage range (1.65V–3.6V) and temperature range (−40°C to +85°C). This is confirmed in the AC characteristics table of the official datasheet (DS-RM24C128DS–115B), where fCLK is specified as 0–1 MHz. At 1 MHz, proper signal integrity requires SDA/SCL pull-up resistors of approximately 2 kΩ and total bus capacitance ≤ 100 pF.

Does RM24C128DS-LMAI-T include hardware write protection?

Yes, RM24C128DS-LMAI-T includes a dedicated hardware write-protect (WP) pin (Pin 7). When WP is tied to VCC, all write operations-including byte write, page write, and OTP security register programming-are inhibited, while read operations remain fully functional. The WP state is sampled at the STOP condition of each write command, ensuring robust protection during power transients or software glitches.

How does the OTP security register in RM24C128DS-LMAI-T function?

The RM24C128DS-LMAI-T contains a 128-byte OTP security register: bytes 0–63 are user-programmable (one-time only), and bytes 64–127 are factory-programmed with a unique identifier. Access uses I²C control code "1011" (vs. "1010" for main memory), and only the lower 7 address bits are effective. Once written, the OTP register is permanently locked - no further writes are possible, even to unwritten bytes within the same 128-byte block.

What package type is used for RM24C128DS-LMAI-T?

RM24C128DS-LMAI-T is supplied in an 8-lead SOIC (Small Outline Integrated Circuit) package with standard JEDEC MS-012AC dimensions (body size 3.9 mm × 4.9 mm, lead pitch 1.27 mm). The "LMAI-T" suffix explicitly denotes this SOIC variant, distinguishing it from TSSOP, UDFN, or WLCSP versions of the same base part number.

Is RM24C128DS-LMAI-T compatible with standard I²C bus protocols?

Yes, RM24C128DS-LMAI-T is fully compliant with standard I²C bus specifications, supporting Standard-mode (100 kHz), Fast-mode (400 kHz), and Fast-mode Plus (1 MHz). It implements open-drain SDA/SCL signaling, acknowledges valid control bytes, respects START/STOP conditions, and handles address matching via E0–E2 pins - enabling seamless integration with any I²C master (e.g., ARM Cortex-M, PIC, ESP32) without protocol translation.