Renesas RM24C128DS-LSNI-B

Overview

RM24C128DS-LSNI-B from Adesto Technologies is a 128Kbit non-volatile serial EEPROM using CBRAM® resistive memory technology, operating from 1.65V to 3.6V with I²C interface up to 1 MHz, 64-byte page size, and integrated 128-byte OTP security register. It delivers ultra-low-energy byte writes (50 nJ), 100,000 write cycles, and >40-year data retention at 125°C - deployed in industrial sensor nodes and secure firmware storage.

For engineers reviewing the RM24C128DS-LSNI-B datasheet, RM24C128DS-LSNI-B pinout, RM24C128DS-LSNI-B application, or RM24C128DS-LSNI-B equivalent, key selection criteria include I²C speed support (100 kHz/400 kHz/1 MHz), OTP register partitioning (64B factory ID + 64B user-programmable), WP pin-controlled array-level write protection, and SOIC/TSSOP/UDFN/WLCSP package compatibility for space-constrained embedded designs.

Technical Context

The RM24C128DS-LSNI-B implements a slave-only 2-wire I²C interface with SDA (open-drain) and SCL (input only), supporting standard, fast, and high-speed modes up to 1 MHz. Device selection uses three hardware address bits (E0–E2), enabling up to eight devices on one bus.

It features dual-address-space access: "1010" control code for 128Kbit EEPROM array (A0–A14 valid), and "1011" for 128-byte OTP Security Register where only lower 6 address bits are effective. Internal address pointer is shared between both spaces, requiring explicit reinitialization when switching contexts.

Key Specifications

Pinout & Package

RM24C128DS-LSNI-B is supplied in an 8-lead SOIC package (3.9 mm × 4.9 mm, 1.27 mm pitch), RoHS-compliant and halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT24C128C-SSHL-T and M95128-DFMN6TP, RM24C128DS-LSNI-B uniquely combines I²C compatibility, 100k-cycle endurance across full temperature range, and factory/user OTP partitioning - making it the sole option for secure, long-life, low-energy embedded NVM where bus protocol, reliability, and identity binding are jointly constrained.

Availability

RM24C128DS-LSNI-B is available at Aetrix Electronics and suitable for industrial sensor calibration, secure firmware vaulting, low-power IoT logging, automotive body control, and medical device configuration storage requiring stable component supply and long-term lifecycle assurance.

Supply support for RM24C128DS-LSNI-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Adesto Technologies (acquired by Dialog Semiconductor in 2020, now part of Renesas Electronics) specialized in low-power, high-reliability non-volatile memory solutions for resource-constrained embedded systems.

The RM24C128DS product line was designed specifically for applications demanding robust data retention, ultra-low write energy, and hardware-enforced security - targeting industrial, medical, and automotive edge devices where traditional EEPROM limitations impede longevity or safety certification.

FAQ

What is the guaranteed data retention period for RM24C128DS-LSNI-B at elevated temperature?

RM24C128DS-LSNI-B guarantees >40 years of data retention at 125°C, validated per JEDEC JESD22-A117B. This exceeds standard EEPROM specifications and ensures reliability in under-hood automotive or high-temp industrial deployments where ambient temperatures routinely exceed 85°C.

Does RM24C128DS-LSNI-B support true random-access byte writes without page boundary constraints?

Yes. RM24C128DS-LSNI-B supports true byte-write operations anywhere in the 128Kbit array without requiring read-modify-write or full-page erasure. Its CBRAM® architecture enables independent byte-level programming - eliminating the endurance penalty seen in floating-gate EEPROMs during partial-page updates.

How is the 128-byte OTP Security Register structured and protected in RM24C128DS-LSNI-B?

The RM24C128DS-LSNI-B OTP Security Register consists of 128 bytes: bytes 0–63 are user-programmable (one-time only), and bytes 64–127 are factory-programmed with a unique identifier. Once written, the entire register is permanently locked - no further writes are possible, even to unwritten locations.

Can RM24C128DS-LSNI-B operate reliably at 1.65 V while sustaining 1 MHz I²C communication?

Yes. RM24C128DS-LSNI-B is fully specified for 1 MHz I²C operation across its entire 1.65–3.6 V supply range, including at the minimum 1.65 V rail. This allows direct integration with 1.8 V microcontrollers without voltage translation, maintaining timing compliance per I²C specification.

What happens to the internal address pointer when switching between EEPROM array and OTP Security Register access in RM24C128DS-LSNI-B?

The RM24C128DS-LSNI-B uses a single shared internal address pointer for both memory spaces. Accessing either space updates the same pointer - so reading the last byte of the EEPROM array sets the pointer to address 0x2000, which then affects subsequent OTP register reads unless explicitly reinitialized via a new address setup sequence.