Renesas RM24C128DS-LTAI-B

Overview

RM24C128DS-LTAI-B from Adesto Technologies is a 128Kbit serial EEPROM memory IC using CBRAM® resistive non-volatile technology, operating from 1.65V to 3.6V with I²C interface up to 1 MHz, featuring 64-byte page write, 128-byte OTP security register (64 factory-unique + 64 user-programmable), and >40-year data retention at 125°C. It serves as a low-energy, high-endurance configuration and calibration storage device in industrial sensors and secure IoT edge nodes.

For engineers reviewing the RM24C128DS-LTAI-B datasheet, RM24C128DS-LTAI-B pinout, RM24C128DS-LTAI-B application, or RM24C128DS-LTAI-B equivalent, key selection considerations include its 100,000 write cycles across full temperature range, 50 nJ byte-write energy, 3 ms page-write time, WP-enabled hardware write protection, and support for up to eight devices on one I²C bus via E0/E1/E2 addressing.

Technical Context

The RM24C128DS-LTAI-B implements a slave-only 2-wire I²C interface with SCL up to 1 MHz and open-drain SDA requiring external pull-up. Its internal address pointer supports Current Address, Random, and Sequential Read modes - with sequential reads capable of streaming the full 128 Kbit memory in one operation.

It integrates three external enable pins (E0, E1, E2) that form the upper bits of the I²C control byte (1010xxxR/W), enabling up to eight devices on a shared bus. The OTP Security Register uses a separate control code (1011xxxR/W) and masks upper address bits, restricting access to 128 bytes (0–127), where addresses 0–63 are user-programmable and 64–127 are factory-programmed unique identifiers.

Key Specifications

Pinout & Package

RM24C128DS-LTAI-B is packaged in an 8-lead TSSOP (Thin Shrink Small Outline Package), pin-compatible with SOIC-8 and UDFN-8 variants. Pin functions are electrically identical across packages.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT24C128C-SSHL-T and M95128-DRMN6TP/K, the RM24C128DS-LTAI-B delivers superior endurance stability across temperature, integrated OTP identity, and deterministic low-energy writes - making it optimal for secure, long-life, low-voltage I²C systems where write-cycle longevity and device authenticity are design-critical.

Availability

RM24C128DS-LTAI-B is available at Aetrix Electronics and suitable for industrial sensor calibration, secure IoT edge node identity, medical diagnostic instrument logging, and automotive body control module settings requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for RM24C128DS-LTAI-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Adesto Technologies (acquired by Dialog Semiconductor in 2020, now part of Renesas Electronics) specialized in ultra-low-power, high-endurance non-volatile memory solutions based on proprietary CBRAM® technology.

The RM24C128DS-LTAI-B belongs to Adesto's CBRAM®-based serial EEPROM product line, engineered for applications demanding extreme write endurance, minimal energy per write, and integrated security features in space- and power-constrained embedded systems.

FAQ

What is the maximum I²C clock frequency supported by the RM24C128DS-LTAI-B?

The RM24C128DS-LTAI-B supports I²C clock frequencies up to 1 MHz under recommended operating conditions (VCC = 1.65V–3.6V, TA = –40°C to +85°C). This enables high-speed parameter loading and firmware metadata updates. The device remains compatible with standard 100 kHz and 400 kHz modes for backward integration with legacy controllers. Timing compliance is verified per JEDEC JESD22-A117B for CBRAM endurance and AC characteristics.

Does the RM24C128DS-LTAI-B require external level shifting when interfaced with a 1.8V microcontroller?

No, the RM24C128DS-LTAI-B operates natively from 1.65V to 3.6V, so it interfaces directly with 1.8V I²C masters without level shifters. Its VIH threshold is VCC × 0.7 and VIL is VCC × 0.3, ensuring reliable logic recognition at 1.8V (VIH ≥ 1.26V, VIL ≤ 0.54V). Pull-up resistors should be sized appropriately (e.g., 2.2 kΩ) to meet rise-time requirements at 1 MHz.

How is the 128-byte OTP Security Register structured in the RM24C128DS-LTAI-B?

The RM24C128DS-LTAI-B's OTP Security Register is a dedicated 128-byte area: bytes 0–63 are user-programmable (one-time), and bytes 64–127 are factory-programmed with a unique identifier by Adesto. Access uses I²C control code 1011xxxR/W (distinct from EEPROM's 1010xxxR/W), and address bits above A5 are masked - limiting effective addressing to 0–127. Once written, the OTP area cannot be erased or rewritten.

Can multiple RM24C128DS-LTAI-B devices share the same I²C bus? How is addressing managed?

Yes, up to eight RM24C128DS-LTAI-B devices can share one I²C bus using hardware-based addressing via E0, E1, and E2 pins. These pins set the three most significant bits of the 7-bit I²C slave address (control code 1010xxxR/W), allowing unique selection without software address configuration. Each device responds only when its E0/E1/E2 combination matches the corresponding bits in the master's transmitted control byte.

What happens to the RM24C128DS-LTAI-B's internal address pointer during mixed EEPROM and OTP register access?

The RM24C128DS-LTAI-B uses a single shared internal address pointer for both the main EEPROM array and the OTP Security Register. A read or write to either region updates the pointer, affecting subsequent accesses to the other region unless explicitly reinitialized. For example, a Random Read from EEPROM address 0x100 increments the pointer to 0x101; the next Current Address Read from the OTP register will start at OTP address 0x101 (masked to 0x01), not 0x00. Designers must manage pointer state explicitly in multi-region firmware flows.