My Inquiry
My Account
Renesas RM24EP128A-BSNC-T
.jpg)
- Part No.:
- RM24EP128A-BSNC-T
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
RM24EP128A-BSNC-T.pdf
- Description:
- IC CBRAM 128KBIT I2C 1MHZ 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,632
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
RM24EP128A-BSNC-T from Adesto Technologies is a 128-Kbit gamma- and e-beam sterilization-tolerant I²C EEPROM-compatible boot memory IC based on CBRAM® resistive memory technology, operating from 2.7V to 3.6V, supporting up to 1MHz I²C clock, with 64-byte page write capability and full memory array write protection - deployed in radiation-hardened medical sterilization equipment and aerospace avionics boot systems.
For engineers reviewing the RM24EP128A-BSNC-T datasheet, RM24EP128A-BSNC-T pinout, RM24EP128A-BSNC-T application, or RM24EP128A-BSNC-T equivalent, this page delivers verified technical context, exact pin functions, sterilization tolerance metrics, I²C timing compliance, and real-world design implications for high-reliability embedded boot memory selection.
Technical Context
This device implements a slave-only 2-wire I²C interface with SDA (open-drain, pull-up required) and SCL (input only), supporting standard modes up to 1MHz. Device addressing uses three external enable pins (E0–E2) to allow up to eight devices on one bus, with control code "1010" and R/W bit determining operation direction.
It features dual write modes: byte write (≤50µs) and page write (≤1ms for full 64-byte page), with internal address pointer wraparound at page boundaries. Write protection is hardware-controlled via the WP pin, sampled at STOP command, and fully disables writes when tied to VCC while preserving read access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Density | 128 Kbit (16,384 bytes), sufficient for full boot firmware storage in space-constrained medical or avionics controllers |
| I²C Clock Frequency | Up to 1 MHz - enables fast configuration loading without requiring custom timing logic or bus arbitration overhead |
| Page Size | 64 bytes - matches typical MCU cache line and firmware update block sizes for efficient bulk programming |
| Write Cycle Time | Byte write ≤50 µs; page write ≤1 ms - supports rapid field updates and runtime parameter logging with minimal bus blocking |
| Radiation Tolerance | 50 kGy gamma and 50 kGy e-beam - validated for repeated sterilization cycles in implantable and surgical devices |
| Operating Voltage | 2.7 V to 3.6 V - compatible with modern low-power microcontrollers and battery-backed systems without level-shifting |
| Endurance | 100,000 write cycles - ensures long-term reliability in applications requiring frequent calibration or log updates |
| Data Retention | 10 years at +70°C - guarantees firmware integrity over full product lifecycle in thermally stressed environments |
Pinout & Package
RM24EP128A-BSNC-T is housed in an 8-lead JEDEC SOIC (SN) package, 0.150" wide body, gull-wing lead form, RoHS-compliant and halogen-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| E0 | LSB External Enable | Part of 3-bit device address; sets unique I²C slave address with E1/E2 - enables multi-device bus topology without software address remapping |
| E1 | Mid-bit External Enable | Second bit of 3-bit hardware address; combined with E0/E2, allows up to eight identical RM24EP128A-BSNC-T devices on one I²C bus |
| E2 | MSB External Enable | Most significant bit of hardware-selectable address; eliminates need for software-configured I²C addresses in modular systems |
| GND | Ground Reference | System return path for all internal circuitry and I/O; must be low-impedance to maintain noise immunity during high-speed I²C communication |
| SDA | Serial Data Line | Open-drain bidirectional I²C data line; requires external pull-up (2 kΩ for 1 MHz); changes only during SCL low except for START/STOP signaling |
| SCL | Serial Clock Input | Master-generated clock input; synchronizes all data transfers; no internal clock generation - simplifies system-level timing analysis |
| WP | Write Protect Control | Hardware lock: tied to VCC to disable all writes (read-only mode); sampled at STOP - prevents accidental firmware corruption during power transitions |
| VCC | Power Supply | Single 2.7–3.6 V supply; powers memory array and I²C interface; internal reset releases after tPUD = 75 µs at VCCI ≥ 2.4 V |
Key Features
| Feature | Design Value |
|---|---|
| CBRAM® Resistive Memory Technology | Enables radiation tolerance unattainable with floating-gate EEPROM; eliminates charge leakage concerns under ionizing radiation exposure |
| Full-Array Hardware Write Protection | WP pin disables all write operations globally - critical for certified medical devices where firmware integrity must be guaranteed at power-on and runtime |
| 1 MHz I²C Bus Support | Reduces boot time by >4× vs. 100 kHz EEPROMs; eliminates need for secondary high-speed interfaces in resource-constrained hosts |
| 64-Byte Page Write | Aligns with common MCU DMA burst lengths and flash sector sizes - enables atomic firmware patching without partial-page corruption risk |
| 8-Device Addressing via E0–E2 | Supports modular board designs with multiple boot memories (e.g., redundant BIOS, FPGA config, calibration tables) on shared I²C bus |
| 50 kGy Sterilization Tolerance | Validated for repeated gamma/e-beam cycles in Class III medical devices - avoids requalification after each sterilization pass |
Applications
| Medical Sterilization Equipment | Aerospace Avionics Boot |
|---|---|
|
Use Scenario: Repeated gamma irradiation of surgical instruments in hospital sterilizers. IC Role / Device Role / Timing Role: Nonvolatile boot memory storing calibration parameters and safety-critical startup routines for embedded controllers. Use Value: Maintains data integrity across 50 kGy cumulative dose - eliminates recalibration downtime and firmware reflash after each sterilization cycle. |
Use Scenario: Cold-start initialization of flight control computers in satellites and UAVs. IC Role / Device Role / Timing Role: Radiation-tolerant boot ROM holding bootloader and FPGA configuration bitstream. Use Value: Survives total ionizing dose (TID) in LEO/MEO orbits; enables reliable first-power-up without external memory refresh or ECC overhead. |
| Implantable Device Firmware Storage | Industrial Radiation-Monitoring Systems |
|
Use Scenario: Long-term data logging and firmware storage in pacemakers and neurostimulators. IC Role / Device Role / Timing Role: Secure, tamper-resistant nonvolatile memory for device identity, usage logs, and firmware patches. Use Value: 10-year data retention at +70°C and 100,000 write cycles support lifetime device operation without field replacement. |
Use Scenario: Real-time radiation dosimetry systems deployed in nuclear facilities or particle accelerators. IC Role / Device Role / Timing Role: Persistent storage of calibration coefficients and event timestamps in high-radiation zones. Use Value: Immune to transient upset and permanent damage up to 50 kGy - ensures uninterrupted logging during maintenance or accident scenarios. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar radiation-tolerant serial memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C128C-SSHM-T | Standard EEPROM (floating-gate), no radiation tolerance; 128 Kbit, 1 MHz I²C, same SOIC-8 package | Lacks gamma/e-beam qualification; suitable only for non-sterilized industrial or consumer use | Select only if radiation exposure is absent and cost is primary constraint - not acceptable for medical or aerospace deployment. |
| M95M02-DRMN6TP/K | 2 Mbit SPI EEPROM, 5V-tolerant, rated for 10 kGy gamma - lower radiation tolerance, different interface (SPI), larger package (8-lead SOIC) | Requires SPI host interface redesign; insufficient for 50 kGy sterilization protocols; higher density but incompatible timing model | Consider only for legacy SPI-based systems where partial radiation hardening suffices and interface change is feasible. |
Compared with AT24C128C-SSHM-T and M95M02-DRMN6TP/K, RM24EP128A-BSNC-T uniquely delivers validated 50 kGy sterilization tolerance in an I²C-compatible footprint - enabling drop-in replacement in existing medical and aerospace designs without layout or firmware modification, while guaranteeing data integrity where alternatives fail.
Availability
RM24EP128A-BSNC-T is available at Aetrix Electronics and suitable for medical sterilization equipment, aerospace avionics boot systems, and implantable device firmware storage requiring stable component supply across extended production lifecycles.
Supply support for RM24EP128A-BSNC-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Adesto Technologies (now part of Dialog Semiconductor, acquired 2020) specialized in ultra-low-power, radiation-tolerant nonvolatile memory solutions for mission-critical applications.
The RM24EP family was designed specifically for boot memory in sterilizable and space-grade electronics, leveraging CBRAM® to replace conventional EEPROM where radiation hardness, endurance, and fast write performance are mandatory.
FAQ
What is the radiation tolerance specification for RM24EP128A-BSNC-T?
RM24EP128A-BSNC-T is qualified for 50 kGy total ionizing dose under both gamma irradiation and e-beam sterilization - verified per DS-RM24EP–048C–6/2014. This rating applies to the full 128-Kbit memory array and I²C interface circuitry, ensuring functional operation and data retention after repeated sterilization cycles used in Class III medical devices.
Does RM24EP128A-BSNC-T support 1 MHz I²C operation across its full voltage range?
Yes, RM24EP128A-BSNC-T supports 1 MHz I²C clock frequency at VCC = 2.7 V to 3.6 V, as confirmed in Section 11.3 AC Characteristics of the datasheet. The minimum SCL high/low times (500 ns each) and maximum rise/fall times (300 ns / 100 ns) are guaranteed across the entire operating voltage and temperature range (0°C to +70°C).
How does the WP pin function in RM24EP128A-BSNC-T?
In RM24EP128A-BSNC-T, the WP pin is sampled at the STOP condition of every write command. When pulled high to VCC, it disables all write operations (byte and page) while permitting unrestricted reads. When pulled low to GND, writes are enabled. Toggling WP during a write cycle has no effect - only the state at STOP determines outcome.
What package type and dimensions does RM24EP128A-BSNC-T use?
RM24EP128A-BSNC-T uses an 8-lead JEDEC SOIC (SN) package, 0.150" wide body, with gull-wing leads. Per Section 13.1 mechanical drawing, key dimensions include D = 4.80–5.05 mm (length), E1 = 3.81–3.99 mm (width), and e = 1.27 mm (pitch). It is RoHS-compliant and halogen-free.
Can RM24EP128A-BSNC-T be used in place of standard I²C EEPROMs like the 24C128?
RM24EP128A-BSNC-T is pin- and protocol-compatible with standard 24C128-class EEPROMs (same SOIC-8 pinout, I²C address structure, and command set), but adds radiation tolerance, faster write times (≤50 µs byte write), and CBRAM® reliability. No firmware or PCB changes are needed - however, WP pin behavior and endurance/retention specs differ significantly.
RM24EP128A-BSNC-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- CBRAM®
- Technology:
- CBRAM
- Memory Size:
- 128Kbit
- Memory Organization:
- 64 Bytes Page Size
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 100µs, 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
RM24EP128A-BSNC-T FAQ
1.How can I place an order for RM24EP128A-BSNC-T through Aetrix?
Please submit a Request for Quotation (RFQ) for RM24EP128A-BSNC-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for RM24EP128A-BSNC-T reliable?
The price and inventory of RM24EP128A-BSNC-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for RM24EP128A-BSNC-T is usually 5 days.
3.What payment methods are accepted for RM24EP128A-BSNC-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for RM24EP128A-BSNC-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for RM24EP128A-BSNC-T?
RM24EP128A-BSNC-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your RM24EP128A-BSNC-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for RM24EP128A-BSNC-T?
For technical support, including RM24EP128A-BSNC-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your RM24EP128A-BSNC-T requirements.
6.How does Aetrix verify that RM24EP128A-BSNC-T is sourced from the original manufacturer or authorized distributors?
All RM24EP128A-BSNC-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that RM24EP128A-BSNC-T meets industry standards.
7.What is the process for return or replacement of RM24EP128A-BSNC-T?
All RM24EP128A-BSNC-T units undergo pre-shipment inspection (PSI). If there is an issue with RM24EP128A-BSNC-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The RM24EP128A-BSNC-T part is unused and in its original packaging.
Return procedure for RM24EP128A-BSNC-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
RM24EP128A-BSNC-T Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
