Renesas RM25C64C-BSNC-B

Overview

RM25C64C-BSNC-B from Adesto Technologies is a 64 Kbit non-volatile serial EEPROM memory IC based on CBRAM® resistive switching technology, operating from 1.65V to 3.6V supply, supporting SPI modes 0 and 3, with 10 MHz fast read capability and 32-byte page write in 1 ms - deployed in industrial sensor nodes for firmware parameter storage.

For engineers reviewing the RM25C64C-BSNC-B datasheet, RM25C64C-BSNC-B pinout, RM25C64C-BSNC-B application, or RM25C64C-BSNC-B equivalent, key selection considerations include its ultra-low 2.2 µA power-down current, 100,000 write-cycle endurance, 10-year data retention, and hardware/software write protection via WP pin and Status Register bits BP0/BP1/SRWD.

Technical Context

This device implements a 4-wire SPI interface (CS, SDO, SDI, SCK) with dual read modes: normal read up to 1.6 MHz and fast read up to 10 MHz. It uses internal self-timed erase/write cycles and supports both byte-level (25 µs) and 32-byte page-level (1 ms) programming.

The memory array is organized as 8,192 × 8 bits, accessed via 16-bit addresses (A15–A0), with only A0–A12 used for the 64 Kbit density. Block protection is configurable via BP0/BP1 bits to lock top ¼ (4 KB), top ½ (8 KB), or full array, while SRWD enables hardware write protection of the Status Register when WP is low.

Key Specifications

Pinout & Package

RM25C64C-BSNC-B is housed in an 8-lead SOIC package (3.9 mm × 4.9 mm, 1.27 mm pitch), RoHS-compliant and halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT25DF041A-SSHN-B and M95M02-DRMN6TP/K, RM25C64C-BSNC-B delivers optimal balance of ultra-low write energy (50 nJ), 10 MHz read speed, and precise 64 Kbit capacity - avoiding over-provisioning while enabling battery-powered edge nodes with 10-year data integrity.

Availability

RM25C64C-BSNC-B is available at Aetrix Electronics and suitable for industrial sensor nodes, medical diagnostics equipment, smart metering infrastructure, and automotive body control modules requiring stable component supply across multi-year production cycles.

Supply support for RM25C64C-BSNC-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Adesto Technologies (acquired by Dialog Semiconductor in 2020, now part of Renesas) specialized in ultra-low-power, high-reliability non-volatile memory solutions for constrained-edge applications.

The RM25C-Series was designed specifically for energy-harvesting and battery-operated IoT endpoints, leveraging CBRAM® to eliminate erase-before-write latency and reduce write energy by orders of magnitude versus floating-gate EEPROM.

FAQ

What is the maximum clock frequency supported by RM25C64C-BSNC-B in fast read mode?

The RM25C64C-BSNC-B supports a maximum SCK clock frequency of 10 MHz in fast read mode, enabling high-speed sequential access to the full 64 Kbit memory array. This is double the 1.6 MHz limit of normal read mode and is achieved using a dedicated FREAD instruction (0Bh) with one dummy byte. The 10 MHz capability allows sub-millisecond full-memory reads, critical for time-sensitive configuration loading in RM25C64C-BSNC-B-based systems.

How does the RM25C64C-BSNC-B implement write protection?

The RM25C64C-BSNC-B provides dual-layer write protection: hardware-based via the WP pin (active-low) combined with the SRWD bit in the Status Register, and software-based using BP0/BP1 bits to lock memory blocks (top ¼, top ½, or full array). The WEL bit must also be set via WREN instruction before any write/erase. This layered scheme ensures robust immunity against accidental writes during power transitions or firmware bugs in RM25C64C-BSNC-B deployments.

What is the page size and write time for RM25C64C-BSNC-B?

The RM25C64C-BSNC-B has a fixed page size of 32 bytes, and a typical page write cycle time of 1 ms. This is significantly faster than conventional EEPROMs (4–6× improvement), due to CBRAM®'s direct-write architecture eliminating erase overhead. Byte writes complete in 25 µs. These timings are self-timed and do not require external polling beyond checking the WIP bit in the Status Register - a key efficiency advantage in RM25C64C-BSNC-B firmware design.

Does RM25C64C-BSNC-B support SPI mode 3, and how is it configured?

Yes, RM25C64C-BSNC-B supports both SPI mode 0 (CPOL=0, CPHA=0) and mode 3 (CPOL=1, CPHA=1). No configuration is required - the device automatically detects idle SCK polarity on CS assertion. In mode 3, SCK remains high during CS high (standby); data is still latched on rising SCK edges (SDI) and output on falling edges (SDO). This dual-mode compatibility simplifies integration with diverse microcontrollers in RM25C64C-BSNC-B designs.

What is the power consumption of RM25C64C-BSNC-B in ultra-deep power-down mode?

In ultra-deep power-down mode (activated by UDPD command 79h), RM25C64C-BSNC-B draws just 1.6 µA typical at 25°C - lower than standard power-down (2.2 µA) and dramatically less than standby (45–120 µA). All commands except exit sequence are ignored, making it ideal for secure, zero-activity retention in RM25C64C-BSNC-B applications like tamper-evident logging or cryptographic key vaults.