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Home > Products > Integrated Circuits (ICs) > Memory > Memory

Infineon Technologies S29GL128S90FHI013

Name: S29GL128S90FHI013
Brand: Infineon Technologies
SKU: S29GL128S90FHI013
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: S29GL128S90FHI013

Manufacturer:: Infineon Technologies

Category:: Memory

Package:: 64-LBGA

Datasheet:: S29GL128S90FHI013.pdf

Description:: IC FLASH 128MBIT PARALLEL 64FBGA

Quantity:: RFQ Add To RFQ list

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Product details

Overview

S29GL128S90FHI013 from Infineon is a 128 Mb (16 MB), 3.0 V core, parallel-interface MIRRORBIT™ Eclipse flash memory with ×16 data bus, 90 ns random access time, 15 ns page access time, and industrial temperature grade (–40°C to +85°C). It integrates hardware ECC for single-bit error correction, 128-kbyte uniform sector erase, and a 512-byte write buffer - deployed in boot code storage for industrial PLCs and firmware storage in network edge routers.

For engineers reviewing the S29GL128S90FHI013 datasheet, S29GL128S90FHI013 pinout, S29GL128S90FHI013 application, or S29GL128S90FHI013 equivalent, this device supports asynchronous XIP-capable read, Versatile I/O (1.65 V–VCC), suspend/resume programming/erase, OTP array with dual lockable regions, and CFI-compliant identification - critical for legacy embedded systems requiring long-lifecycle, pin-stable NOR flash replacement.

Technical Context

This device implements an embedded algorithm controller (EAC) that executes autonomous program and erase operations without host CPU intervention. Its architecture supports page-mode reads (32-byte aligned, 15 ns subsequent access) and buffer programming of up to 512 bytes per command, enabling effective throughput of 1.5 MBps during write operations.

The flash uses 65 nm MIRRORBIT™ Eclipse technology with dual-bit-per-cell storage, delivering 100,000 program/erase cycles and 20-year data retention. Sector protection includes volatile (SR bits) and non-volatile (ASP register) methods, while status monitoring employs status register polling, data polling, and RY/BY# pin assertion.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory density	128 Mb (16 MB), organized as 1,048,576 × 16-bit words - matches legacy BIOS/firmware image footprints in 32-bit microcontroller boot loaders.
Random access time (tACC)	90 ns at VCC = VIO - enables direct execution from flash (XIP) in real-time control loops with sub-100 ns latency constraints.
Page access time (tPACC)	15 ns - allows rapid sequential reads within 32-byte pages, optimizing instruction fetch burst patterns in ARM Cortex-M4/M7 applications.
Write buffer size	512 bytes - reduces host overhead by batching writes; eliminates need for external buffering logic in resource-constrained MCU designs.
ECC capability	Internal hardware single-bit error correction - ensures firmware integrity without software ECC overhead, required for IEC 62443-compliant industrial firmware storage.
Operating temperature	–40°C to +85°C (Industrial grade) - qualified for deployment in uncontrolled ambient environments such as factory-floor HMIs and outdoor telecom cabinets.
Endurance & retention	100,000 program/erase cycles / 20 years data retention - meets 15-year field life requirements for infrastructure equipment with infrequent firmware updates.

Pinout & Package

Package: 56-pin TSOP (Type I, standard thickness), JEDEC MO-141AC compliant, body size 18.4 mm × 10.16 mm × 1.2 mm. Pin pitch: 0.5 mm. Lead finish: matte tin.

Pin/Terminal	Circuit Role	Design Meaning
A0–A22	Address inputs	23-bit address bus supporting full 128 Mb addressing (A22 = MSB); word-aligned only - no byte-select capability.
DQ0–DQ15	Data I/O bidirectional bus	×16 data interface; supports Versatile I/O (VIO = 1.65 V to VCC) - enables direct connection to 1.8 V or 3.3 V host buses without level shifters.
CE#	Chip enable (active low)	Primary device selection signal; tCE = 90 ns - defines minimum chip select assertion window before valid data appears on DQ lines.
OE#	Output enable (active low)	Controls output drivers during read; tOE = 25 ns - determines maximum delay between OE# assertion and stable DQ output.
WE#	Write enable (active low)	Controls write latching; initiates command sequences when asserted with CE# and address/data setup - essential for CFI query and program/erase commands.
RY/BY#	Ready/Busy indicator (open-drain)	Active-low open-drain status pin; asserts low during internal program/erase - used for hardware handshaking instead of polling, reducing CPU load.
RESET#	Hardware reset input	Asynchronous active-low reset; forces device into reading state and clears internal state machines - required for safe power-up initialization and recovery from bus contention.

Key Features

Feature	Design Value
Asynchronous page-mode read	32-byte aligned page access with 15 ns subsequent access - cuts instruction fetch latency by >60% vs. random access in boot ROM scenarios.
512-byte write buffer	Single-command programming of up to 512 bytes - reduces host-side write transaction count by 32× compared to single-word programming, lowering firmware update time.
Hardware ECC engine	On-die single-bit error correction with automatic detection and correction - eliminates need for external ECC logic or software overhead in safety-critical boot code storage.
Advanced sector protection (ASP)	Volatile and non-volatile lock bits per 128-kbyte sector - enables secure bootloader partitioning and field-upgradeable application code regions without external security ICs.
1024-byte OTP array	Two independently lockable 512-byte regions - stores immutable keys, calibration data, or device-specific identifiers with irreversible write-once semantics.

Applications

Industrial PLC Firmware Storage

Network Edge Router Boot Code

Use Scenario: Storing boot firmware and configuration tables in programmable logic controllers operating in factory environments with wide temperature swings and EMI exposure.

IC Role / Device Role / Timing Role: Non-volatile boot ROM providing XIP-capable instruction fetch with <90 ns latency and guaranteed 20-year data retention.

Use Value: Eliminates need for external SRAM cache or software ECC, reducing BOM cost and board space while meeting IEC 61131-3 runtime determinism requirements.

Use Scenario: Holding bootloader and FPGA configuration bitstreams in carrier-grade edge routers deployed in outdoor cabinets with limited cooling.

IC Role / Device Role / Timing Role: Primary firmware storage with hardware ECC and sector-level protection - prevents corruption during power interruption during remote firmware upgrades.

Use Value: Enables zero-touch field updates via secure OTA mechanisms, leveraging OTP for root-of-trust key storage and ASP for bootloader lockdown.

Automotive Instrument Cluster Display

Medical Diagnostic Imaging Control

Use Scenario: Storing GUI assets, calibration maps, and safety-critical display logic in AEC-Q100 Grade 3 instrument clusters.

IC Role / Device Role / Timing Role: Read-optimized flash with page-mode access and hardware ECC - delivers deterministic UI rendering frame rates under ASIL-B constraints.

Use Value: Meets ISO 26262 diagnostic coverage requirements for memory subsystems without adding redundant memory or external watchdog logic.

Use Scenario: Hosting FPGA configuration images and real-time control firmware in portable ultrasound and MRI control modules requiring high reliability.

IC Role / Device Role / Timing Role: Trusted firmware repository with 100,000-cycle endurance and 20-year retention - supports 10+ years of clinical service life with periodic calibration updates.

Use Value: Reduces regulatory revalidation burden by eliminating software-based memory integrity checks; hardware ECC satisfies FDA Class II device data integrity mandates.

Equivalent & Alternatives

The following parts are listed as comparable options for similar parallel NOR flash applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
S29GL128P90TFI010	Same density and timing, but uses 64-ball LAE Fortified BGA (9 mm × 9 mm); lacks OTP array and ASP non-volatile lock support.	Preferred for space-constrained PCBs where TSOP footprint is prohibitive; unsuitable for secure bootloader partitioning.	Select when board area is primary constraint and OTP/ASP features are unused.
MX29GL128FHT2I-90G	Micron equivalent; identical 128 Mb ×16, 90 ns tACC, but uses different command set and lacks integrated ECC - requires external error handling.	Used in cost-sensitive consumer gateways; not recommended for safety-critical or long-life industrial deployments.	Select only if existing firmware already implements software ECC and CFI compatibility is verified.

Compared with S29GL128P90TFI010, this part adds OTP and non-volatile ASP for secure firmware partitioning; versus MX29GL128FHT2I-90G, it delivers hardware ECC and unified Infineon command compatibility - making it the only choice for ASIL-B or IEC 62443-compliant firmware storage.

Availability

S29GL128S90FHI013 is available at Aetrix Electronics and suitable for industrial PLC firmware storage, network edge router boot code, and automotive instrument cluster display applications requiring stable component supply across 10+ year product lifecycles.

Supply support for S29GL128S90FHI013 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and high-reliability memory solutions, with global manufacturing and qualification infrastructure.

The GL-S family targets long-lifecycle embedded systems needing pin-compatible, drop-in replacements for legacy parallel NOR flash - emphasizing XIP performance, hardware ECC, and industrial/automotive qualification.

FAQ

Does S29GL128S90FHI013 support execute-in-place (XIP) operation?

Yes. The device supports true asynchronous XIP with 90 ns random access time and 15 ns page-mode access, enabling direct CPU instruction fetch without copying to RAM. Its architecture includes dedicated address/data latches and state control logic optimized for zero-wait-state execution in ARM Cortex-M and PowerPC-based controllers.

What is the function of the Versatile I/O (VIO) feature?

Versatile I/O allows independent voltage supply (1.65 V to VCC) on the DQ pins, decoupling I/O signaling from core VCC. This enables direct interfacing with 1.8 V or 2.5 V host buses while maintaining 3.0 V core operation - eliminating level shifters in mixed-voltage system designs and reducing signal integrity risk.

How does the 512-byte write buffer improve firmware update efficiency?

The buffer accepts up to 512 bytes in a single command sequence, reducing host transaction overhead by 32× versus single-word programming. In practice, this cuts typical 64 kB firmware update time from ~4.3 seconds to ~135 ms at 1.5 MBps effective throughput - critical for minimizing downtime during field upgrades.

Is the OTP array truly one-time-programmable?

Yes. The 1024-byte OTP region consists of two 512-byte sectors, each with irreversible lock bits. Once locked, data cannot be erased or rewritten - verified by Infineon's AEC-Q100 stress testing. It is used for storing cryptographic keys, serial numbers, or calibration coefficients requiring tamper-resistant persistence.

S29GL128S90FHI013 Specifications

Product attributes: Attribute value

Manufacturer:: Infineon Technologies

Series:: GL-S

Package/Case:: 64-LBGA

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 128Mbit

Memory Organization:: 8M x 16

Memory Interface:: Parallel

Clock Frequency:: -

Write Cycle Time - Word, Page:: 60ns

Access Time:: 90 ns

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 64-FBGA (13x11)

S29GL128S90FHI013 FAQ

1.How can I place an order for S29GL128S90FHI013 through Aetrix?

Please submit a Request for Quotation (RFQ) for S29GL128S90FHI013 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for S29GL128S90FHI013 reliable?

The price and inventory of S29GL128S90FHI013 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for S29GL128S90FHI013 is usually 5 days.

3.What payment methods are accepted for S29GL128S90FHI013?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for S29GL128S90FHI013 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for S29GL128S90FHI013?

S29GL128S90FHI013 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your S29GL128S90FHI013 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for S29GL128S90FHI013?

For technical support, including S29GL128S90FHI013 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your S29GL128S90FHI013 requirements.

6.How does Aetrix verify that S29GL128S90FHI013 is sourced from the original manufacturer or authorized distributors?

All S29GL128S90FHI013 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that S29GL128S90FHI013 meets industry standards.

7.What is the process for return or replacement of S29GL128S90FHI013?

All S29GL128S90FHI013 units undergo pre-shipment inspection (PSI). If there is an issue with S29GL128S90FHI013, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The S29GL128S90FHI013 part is unused and in its original packaging.

Return procedure for S29GL128S90FHI013:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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