NXP Semiconductors S32K328GHT1MJBST
- Part No.:
- S32K328GHT1MJBST
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
S32K328GHT1MJBST.pdf
- Description:
- S32K328GHT1MJBST
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
S32K328GHT1MJBST from NXP Semiconductors is an ASIL-B dual-core Arm® Cortex-M7 automotive microcontroller operating up to 240 MHz, featuring 8 MB ECC-protected program flash, 1152 KB SRAM (including 192 KB TCM), and integrated QuadSPI supporting up to 2 Gbps with 8-bit data width. It delivers real-time control for body electronics and domain controllers in harsh automotive environments.
For engineers reviewing the S32K328GHT1MJBST datasheet, S32K328GHT1MJBST pinout, S32K328GHT1MJBST application, or S32K328GHT1MJBST equivalent, key selection factors include dual-core deterministic timing, CAN FD support across eight FlexCAN modules, Ethernet AVB/TSN at 1 Gbps, and hardware security engine (HSE_B) with AES acceleration - all validated for -40 °C to 125 °C operation.
Technical Context
The S32K328GHT1MJBST implements two independent Arm Cortex-M7 cores running at 240 MHz each, with separate I/D caches and zero-wait-state TCM RAM to minimize latency in fast control loops. Its memory subsystem includes ECC on all SRAM and flash, plus RWW (Read-While-Write) capability enabling A/B swap for OTA updates.
Timing and safety are enforced via dual PLLs, System Timer Modules (STM), three eMIOS blocks (72 timer channels total), and a centralized Functional Safety Control Unit (FCCU) with ASIL-B compliance. The device integrates BCTU for cross-triggering between ADCs and timers, and XRDC for master-access rights protection across domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual independent Arm Cortex-M7 @ 240 MHz - enables parallel real-time task partitioning without lockstep overhead. |
| Flash Memory | 8 MB program flash with ECC - ensures integrity of boot code and application firmware in automotive ECU deployments. |
| SRAM | 1152 KB SRAM with ECC, including 192 KB TCM - provides low-latency memory for time-critical ISR and control algorithms. |
| QuadSPI Interface | Up to 2 Gbps, 8-bit data width - supports high-speed external flash/RAM expansion for logging, OTA staging, or firmware overlay. |
| Networking | 1 × 1 Gbps Ethernet (AVB/TSN), 8 × FlexCAN (all with CAN FD) - meets modern vehicle domain controller bandwidth and protocol requirements. |
| Analog Peripherals | 3 × 12-bit ADC (24-channel each), 3 × analog comparators with internal 8-bit DAC - enables sensor fusion and closed-loop actuator control. |
| Operating Range | -40 °C to 125 °C ambient, 2.97 V to 5.5 V supply - qualified for under-hood and powertrain-adjacent automotive locations. |
| Security | HSE_B hardware security engine with AES acceleration - offloads cryptographic operations while maintaining side-channel resistance per Evita Full. |
Pinout & Package
Package: MAPBGA437 (17 × 17 mm, 0.8 mm pitch, exposed thermal pad). Pin count and signal assignment align with S32K3xx family pin compatibility across MAPBGA437, HDQFP172, and LQFP48 variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA / VSSA | Analog power / ground | Isolated analog supply domain for ADC/CMP reference stability; requires dedicated filtering per layout guidelines. |
| ENET0_RXD0–3 / TXD0–3 | Ethernet PHY interface | Differential 100BASE-TX signaling pins supporting AVB/TSN timestamping and traffic shaping. |
| FLEXCAN0_TX / RX | CAN FD physical layer I/O | Direct connection to CAN transceiver; supports bit rates up to 5 Mbps with flexible data phase configuration. |
| QSPI0_SCLK / SIO0–3 | QuadSPI clock and data lines | High-speed serial interface for external memory; SIO0–3 support single/dual/quad I/O modes with configurable drive strength. |
| JTAG_TCK / TMS / TDI / TDO | Debug interface | 2-pin SWD-compatible JTAG port for production programming and run-time trace via Serial Wire Viewer (SWV). |
| WAKEUP0–59 | Low-power wakeup input | Configurable GPIO pins capable of waking CPU from STANDBY mode; supports edge-triggered interrupt generation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Cortex-M7 cores @ 240 MHz | Enables asymmetric task distribution - one core for safety-critical control, the other for diagnostics or communication stack processing. |
| ASIL-B compliant functional safety architecture | Includes FCCU, SWT, CRC, ECC on all memories, and centralized error detection - reduces FMEDA effort for ISO 26262 compliance. |
| Hardware Security Engine (HSE_B) | Accelerates AES-256, RSA-4096, and ECC-521; includes firmware-upgradable crypto library and physical side-channel protections. |
| QuadSPI with 2 Gbps throughput | Supports external XIP execution and secure OTA staging - eliminates need for additional NOR/NAND controllers in gateway designs. |
| Three 24-channel 12-bit ADCs with BCTU | Allows synchronized sampling across multiple sensors (e.g., motor phase currents + temperature) with sub-microsecond trigger alignment. |
| FlexIO module (32 channels) | Programmable logic for custom protocols (SENT, PWM, I²S, SPI) - replaces discrete glue logic and reduces BOM cost in sensor interface applications. |
Applications
| Body Control Module (BCM) | Vehicle Domain Controller |
|---|---|
|
Use Scenario: Centralized management of lighting, door locks, window lifts, and seat controls in modern vehicles. IC Role / Device Role / Timing Role: Primary MCU executing real-time PWM dimming, LIN slave emulation, and CAN FD gateway routing. Use Value: Dual-core isolation allows concurrent execution of safety-monitored body functions and non-safety diagnostics without resource contention. |
Use Scenario: Aggregation and orchestration of ADAS, infotainment, and chassis subsystems in zonal architectures. IC Role / Device Role / Timing Role: High-bandwidth domain orchestrator with 1 Gbps Ethernet TSN scheduling and 8× CAN FD channel bridging. Use Value: Integrated QuadSPI and 1152 KB SRAM enable local OTA staging and deterministic packet buffering for time-sensitive network traffic. |
| Electric Power Steering (EPS) Support MCU | Advanced Gateway Module |
|
Use Scenario: Secondary controller handling sensor preprocessing, fault logging, and communication with primary EPS MCU. IC Role / Device Role / Timing Role: Real-time co-processor using eMIOS PWM timers and ADC oversampling for torque sensor signal conditioning. Use Value: 192 KB TCM RAM and zero-wait I/D cache ensure <1 µs ISR latency for critical fault detection and fail-safe activation. |
Use Scenario: Secure vehicle-to-cloud and vehicle-to-vehicle communication hub with firewall and protocol translation. IC Role / Device Role / Timing Role: Cryptographic offload engine leveraging HSE_B for TLS handshake acceleration and secure boot verification. Use Value: Hardware-accelerated AES and ECC reduce CPU load by >70% versus software-only implementations, preserving bandwidth for routing tasks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| S32K344 | ASIL-D lockstep dual-core Cortex-M7 @ 160 MHz; 4 MB flash; no Ethernet or QuadSPI | Targeted at safety-critical steering/braking ECUs requiring higher ASIL rating but lower bandwidth | Select when functional safety certification to ASIL-D is mandatory and Ethernet/QuadSPI are unnecessary. |
| S32K324 | ASIL-B dual-core Cortex-M7 @ 160 MHz; 4 MB flash; 100 Mbps Ethernet; 480 Mbps QuadSPI | Cost-optimized variant for mid-tier domain controllers with reduced memory and bandwidth needs | Choose when 8 MB flash and 1 Gbps Ethernet are not required, and BOM cost reduction is prioritized. |
Compared with S32K328GHT1MJBST, S32K344 provides higher safety assurance at lower performance and peripheral count, while S32K324 offers similar dual-core architecture but with halved flash capacity, slower Ethernet, and reduced QuadSPI speed - making both suitable for tiered product families where scalability matters.
Availability
S32K328GHT1MJBST is available at Aetrix Electronics and suitable for automotive body electronics, domain controllers, and advanced gateways requiring stable component supply, long lifecycle support, and AEC-Q100 Grade 1 qualification.
Supply support for S32K328GHT1MJBST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade MCUs.
The S32K3xx product line was designed specifically for next-generation automotive domain controllers and zonal architectures, emphasizing ASIL-B/D compliance, hardware security, and scalable multicore performance in harsh environments.
FAQ
What is the maximum operating frequency of the S32K328GHT1MJBST?
The S32K328GHT1MJBST features two independent Arm Cortex-M7 cores, each operating at up to 240 MHz. This frequency is fully supported across the specified voltage range (2.97 V to 5.5 V) and ambient temperature range (-40 °C to 125 °C), enabling deterministic real-time execution for automotive control applications. The S32K328GHT1MJBST achieves this performance with zero-wait-state TCM and dual-level cache architecture.
Does the S32K328GHT1MJBST support CAN FD, and how many channels are available?
Yes, the S32K328GHT1MJBST integrates eight FlexCAN modules, and all channels support CAN FD with data rates up to 5 Mbps. Each module includes dedicated message RAM, acceptance filtering, and loopback/self-test modes. This capability makes the S32K328GHT1MJBST suitable for high-bandwidth vehicle networks such as domain controllers and advanced gateways requiring multi-bus isolation.
What package type is used for the S32K328GHT1MJBST, and what are its thermal characteristics?
The S32K328GHT1MJBST uses a MAPBGA437 package (17 mm × 17 mm, 0.8 mm pitch) with an exposed thermal pad. This package supports junction-to-case thermal resistance (θJC) of ≤ 3.5 °C/W when mounted with recommended PCB copper area and thermal vias. The exposed pad must be soldered to a solid ground plane for optimal thermal dissipation in automotive under-hood applications.
Is the S32K328GHT1MJBST qualified for automotive use, and what standards does it meet?
Yes, the S32K328GHT1MJBST is AEC-Q100 Grade 1 qualified (-40 °C to 125 °C) and designed to meet ISO 26262 ASIL-B requirements. It includes hardware safety mechanisms such as ECC on all memories, dual watchdog timers, centralized error detection, and lockstep-capable peripherals. These features are documented in NXP's FS diagnostic library and safety manual for the S32K3xx series.
Does the S32K328GHT1MJBST include hardware security features beyond basic encryption acceleration?
Yes, the S32K328GHT1MJBST integrates the HSE_B hardware security engine, which supports AES-256, RSA-4096, and ECC-521 acceleration, plus TRNG/PRNG, secure boot, key provisioning, and side-channel resistant implementation meeting Evita Full requirements. It also includes XRDC for memory access control and VIRT_WRAPPER for I/O protection - all verified in NXP's Common Criteria EAL5+ certified firmware stack.
S32K328GHT1MJBST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- S32K3
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, Ethernet, FlexIO, I2C, LINbus, QSPI, SAI, SENT, SPI, UART/USART
- Peripherals:
- DMA, I2S, WDT
- Number of I/O:
- 218
- Program Memory Size:
- 8MB (8M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 1.125M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.97V ~ 5.5V
- Data Converters:
- A/D 24x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
S32K328GHT1MJBST FAQ
1.How can I place an order for S32K328GHT1MJBST through Aetrix?
Please submit a Request for Quotation (RFQ) for S32K328GHT1MJBST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for S32K328GHT1MJBST reliable?
The price and inventory of S32K328GHT1MJBST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for S32K328GHT1MJBST is usually 5 days.
3.What payment methods are accepted for S32K328GHT1MJBST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for S32K328GHT1MJBST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for S32K328GHT1MJBST?
S32K328GHT1MJBST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your S32K328GHT1MJBST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for S32K328GHT1MJBST?
For technical support, including S32K328GHT1MJBST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your S32K328GHT1MJBST requirements.
6.How does Aetrix verify that S32K328GHT1MJBST is sourced from the original manufacturer or authorized distributors?
All S32K328GHT1MJBST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that S32K328GHT1MJBST meets industry standards.
7.What is the process for return or replacement of S32K328GHT1MJBST?
All S32K328GHT1MJBST units undergo pre-shipment inspection (PSI). If there is an issue with S32K328GHT1MJBST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The S32K328GHT1MJBST part is unused and in its original packaging.
Return procedure for S32K328GHT1MJBST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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