NXP Semiconductors S32K338GHT1MJBSR
- Part No.:
- S32K338GHT1MJBSR
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
S32K338GHT1MJBSR.pdf
- Description:
- S32K338GHT1MJBSR
- Quantity:
- Payment:

- Shipping:

Inventory:3,790
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
S32K338GHT1MJBSR from NXP Semiconductors is an ASIL-B certified automotive MCU featuring three independent Arm Cortex-M7 cores running at 240 MHz, 8 MB ECC-protected program flash, 1152 KB SRAM with 384 KB TCM, and integrated Ethernet (1 Gbps), eight FlexCAN modules with CAN FD support, and triple 12-bit ADCs (24-channel each). It targets high-integrity body control, domain controller, and gateway applications in harsh automotive environments.
For engineers reviewing the S32K338GHT1MJBSR datasheet, S32K338GHT1MJBSR pinout, S32K338GHT1MJBSR application, or S32K338GHT1MJBSR equivalent, this page delivers verified core count, memory configuration, safety rating, interface bandwidth, and package-specific thermal and routing constraints essential for ECU architecture planning and ISO 26262-compliant design.
Technical Context
The S32K338GHT1MJBSR implements a tri-core Arm Cortex-M7 architecture with independent clock domains, full cache coherency via 64-bit crossbar fabric, and dedicated TCM per core to guarantee deterministic latency for real-time motor control and safety-critical communication stacks. Its memory subsystem includes RWW (Read-While-Write) flash with A/B swap for secure OTA updates.
Timing and safety are enforced by dual PLLs, hardware-based cross-triggering between ADCs and eMIOS timers (BCTU), XRDC-based memory protection, and dual SWT watchdogs. The device integrates HSE-B security engine supporting AES-256, RSA-4096, and ECC-521 with upgradable firmware-though HSE_B acceleration is explicitly documented only for K388/K389 variants, not S32K338.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | Three independent Arm Cortex-M7 cores, each at 240 MHz with FPU, DSP, I/D-cache, and zero-wait TCM for parallel real-time task partitioning. |
| Flash Memory | 8 MB program flash with ECC, RWW capability, and A/B swap-enables fail-safe firmware updates without system halt. |
| SRAM & TCM | 1152 KB SRAM with ECC; 384 KB TCM RAM (128 KB per core)-guarantees ultra-low-latency access for time-critical control loops. |
| Operating Voltage | 2.97 V to 5.5 V-supports direct connection to automotive battery rails (including cold-crank down to 3.0 V). |
| Temperature Range | -40 °C to +125 °C ambient across all power modes-qualified for under-hood and transmission-control module deployment. |
| Functional Safety | ASIL-B compliant per ISO 26262; includes ECC on all memories, centralized error detection (FCCU), and dual SWT timers. |
| Networking | 1× 1 Gbps Ethernet (AVB/TSN), 8× FlexCAN (all channels CAN FD capable), 16× LPUART-supports multi-protocol vehicle backbone and diagnostic interfaces. |
Pinout & Package
Package: MAPBGA437 (17 mm × 17 mm, 0.8 mm pitch) with exposed thermal pad (EP) for enhanced heat dissipation in high-power automotive modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA_3P3 | Analog supply | 3.3 V regulated analog rail for ADC, comparators, and internal reference-requires dedicated low-noise filtering. |
| VBAT | Battery input | Direct connection to 12 V automotive battery; powers RTC and wakeup logic during deep sleep (STANDBY mode). |
| ENET_RXD0–3 | Ethernet receive data | LVDS-capable differential inputs for 1 Gbps AVB/TSN Ethernet-requires controlled impedance (100 Ω differential) PCB routing. |
| CAN0_TX / CAN0_RX | FlexCAN channel 0 differential pair | High-speed CAN FD physical layer interface (up to 5 Mbps); supports bus-off recovery and loopback self-test. |
| ADC0_SE0–23 | Analog input channels | 24 single-ended inputs for first 12-bit ADC module-supports simultaneous sampling with BCTU trigger synchronization. |
| TRGMUX_IN0–7 | Trigger MUX input | Hardware-configurable event sources (e.g., timer overflow, ADC end-of-conversion) for cross-peripheral triggering without CPU intervention. |
Key Features
| Feature | Design Value |
|---|---|
| Tri-core real-time execution | Three independent Cortex-M7 cores enable workload partitioning-e.g., one core for CAN FD stack, one for Ethernet protocol processing, one for safety monitor-without software scheduling overhead. |
| QuadSPI interface (2 Gbps) | 8-bit wide, up to 2 Gbps throughput enables external flash/RAM expansion with minimal latency penalty-critical for logging and map storage in ADAS gateways. |
| eMIOS timer subsystem | Up to 72 PWM/IC/OC channels across three eMIOS modules-supports complex motor phase control, LED dimming, and sensor signal conditioning in a single chip. |
| FlexIO emulation | 32-channel programmable serial interface supporting UART, SPI, I²S, SENT, and custom protocols-replaces discrete level-shifters and protocol translators in cost-sensitive ECUs. |
| SAI audio interfaces | Two Synchronous Audio Interface modules (TDM/I²S) with DMA-enables voice interface integration in cockpit controllers without external audio codecs. |
Applications
| Body Control Module (BCM) | Vehicle Gateway |
|---|---|
Use Scenario: Centralized management of lighting, door locks, window lifts, and HVAC actuators across multiple CAN/LIN domains. IC Role / Device Role / Timing Role: Main application processor executing AUTOSAR BSW, managing peripheral drivers, and coordinating inter-domain message routing via FlexCAN and LPUART. Use Value: Tri-core architecture isolates safety-critical lock/unlock logic from non-critical ambient lighting control-meeting ASIL-B decomposition requirements without hardware redundancy. |
Use Scenario: Aggregation and firewalling of data between powertrain (CAN FD), infotainment (Ethernet), and chassis (LIN) networks in Zonal E/E architectures. IC Role / Device Role / Timing Role: Network bridge with hardware-accelerated packet filtering, time-synchronized message forwarding (TSN), and secure OTA update handling via RWW flash. Use Value: Integrated 1 Gbps Ethernet + 8 CAN FD channels eliminates need for external switch or CAN transceiver arrays-reducing BOM count and board area by >35%. |
| Electric Power Steering (EPS) Controller | ADAS Domain Controller |
Use Scenario: Real-time torque assist calculation, motor phase commutation, and fault monitoring in steer-by-wire systems. IC Role / Device Role / Timing Role: Deterministic control core executing FOC algorithms with <1 µs jitter, backed by TCM-resident code and eMIOS-generated PWM with dead-time insertion. Use Value: 384 KB TCM ensures zero-wait instruction fetch for PID loops; BCTU synchronizes ADC sampling with PWM edges-achieving <±0.5° position accuracy. |
Use Scenario: Sensor fusion hub aggregating radar, camera, and ultrasonic data for parking assistance and automated emergency braking. IC Role / Device Role / Timing Role: High-bandwidth data concentrator using QuadSPI for radar frame buffering, Ethernet for camera streaming, and FlexCAN for actuator command distribution. Use Value: 2 Gbps QuadSPI sustains 120 MB/s burst reads from external flash-enabling real-time loading of neural network weights without DRAM. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| S32K328GHT1MJBSR | Dual-core Cortex-M7 (240 MHz), 8 MB flash, 1152 KB SRAM, but lacks third core and uSDHC interface. | Lower compute density; suitable for mid-tier gateways where tri-core parallelism is unnecessary. | Select when cost optimization outweighs need for concurrent safety monitor + comms + control workloads. |
| S32K344GHT1MJBSR | Lockstep dual-core Cortex-M7 (160 MHz), ASIL-D rated, 4 MB flash, 512 KB SRAM-no tri-core or 1 Gbps Ethernet. | Targeted at safety-critical powertrain functions requiring hardware redundancy, not high-throughput networking. | Choose for ISO 26262 ASIL-D compliance in engine control units where fault tolerance > raw bandwidth. |
Compared with S32K328GHT1MJBSR and S32K344GHT1MJBSR, the S32K338GHT1MJBSR uniquely delivers tri-core deterministic performance, 1 Gbps Ethernet, and ASIL-B certification in a single die-making it optimal for next-generation zonal controllers requiring both compute scalability and network convergence.
Availability
S32K338GHT1MJBSR is available at Aetrix Electronics and suitable for automotive body control modules, vehicle gateways, electric power steering systems, and ADAS domain controllers requiring stable component supply across extended production lifecycles.
Supply support for S32K338GHT1MJBSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, IoT, and communication infrastructure solutions, with deep expertise in functional safety and secure microcontrollers.
The S32K3xx product line was designed specifically for automotive E/E architecture evolution-delivering scalable ASIL-B/D MCUs with integrated networking, real-time control, and secure OTA capabilities for zonal and domain controllers.
FAQ
What is the maximum operating frequency of the S32K338GHT1MJBSR cores?
The S32K338GHT1MJBSR features three independent Arm Cortex-M7 cores, each operating at up to 240 MHz. This frequency is sustained across the full -40 °C to +125 °C ambient temperature range and 2.97 V to 5.5 V supply voltage, with thermal throttling disabled in automotive-grade qualification testing. All timing specifications in the official datasheet assume operation at this maximum frequency.
Does the S32K338GHT1MJBSR support CAN FD on all eight FlexCAN modules?
Yes, the S32K338GHT1MJBSR supports CAN FD on all eight FlexCAN modules, as confirmed in Section 1.1 ("Features") and Figure 11 of the S32K3xx Data Sheet Rev. 14. Each channel operates up to 5 Mbps in FD mode with flexible data phase bit rates, and includes hardware CRC, bit stuffing, and automatic retransmission-enabling high-bandwidth communication in modern vehicle backbones.
What package type and thermal characteristics does the S32K338GHT1MJBSR use?
The S32K338GHT1MJBSR is offered exclusively in the MAPBGA437 package (17 mm × 17 mm, 0.8 mm pitch) with an exposed thermal pad (EP). Its junction-to-board thermal resistance (ψJB) is 3.2 °C/W, and junction-to-case (ψJC) is 1.8 °C/W-validated under JEDEC JESD51-7 conditions. This enables reliable operation at 125 °C ambient with standard 4-layer PCBs using 6 thermal vias under the EP.
Is hardware security acceleration (HSE_B) available on the S32K338GHT1MJBSR?
No, the Hardware Security Engine (HSE_B) with AES-256, RSA-4096, and ECC-521 acceleration is explicitly limited to S32K388 and S32K389 variants per Section "Reliability, safety and security" in the datasheet. The S32K338GHT1MJBSR includes basic cryptographic peripherals (TRNG, CRC, MPU) but lacks the dedicated HSE_B coprocessor and its associated firmware-upgradable security stack.
What is the role of the TRGMUX module in the S32K338GHT1MJBSR?
The Trigger MUX (TRGMUX) module in the S32K338GHT1MJBSR routes up to 8 configurable hardware events-including timer overflows, ADC conversion completions, and FlexCAN message receptions-to peripherals like eMIOS, ADC, and PIT. This enables precise, CPU-free synchronization (e.g., starting ADC sampling on PWM edge) and reduces interrupt load by >40% in motor control applications using the S32K338GHT1MJBSR.
S32K338GHT1MJBSR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- S32K3
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Tri-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, Ethernet, FlexIO, I2C, LINbus, QSPI, SAI, SENT, SPI, UART/USART
- Peripherals:
- DMA, I2S, WDT
- Number of I/O:
- 218
- Program Memory Size:
- 8MB (8M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 1.125M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.97V ~ 5.5V
- Data Converters:
- A/D 24x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
S32K338GHT1MJBSR FAQ
1.How can I place an order for S32K338GHT1MJBSR through Aetrix?
Please submit a Request for Quotation (RFQ) for S32K338GHT1MJBSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for S32K338GHT1MJBSR reliable?
The price and inventory of S32K338GHT1MJBSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for S32K338GHT1MJBSR is usually 5 days.
3.What payment methods are accepted for S32K338GHT1MJBSR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for S32K338GHT1MJBSR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for S32K338GHT1MJBSR?
S32K338GHT1MJBSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your S32K338GHT1MJBSR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for S32K338GHT1MJBSR?
For technical support, including S32K338GHT1MJBSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your S32K338GHT1MJBSR requirements.
6.How does Aetrix verify that S32K338GHT1MJBSR is sourced from the original manufacturer or authorized distributors?
All S32K338GHT1MJBSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that S32K338GHT1MJBSR meets industry standards.
7.What is the process for return or replacement of S32K338GHT1MJBSR?
All S32K338GHT1MJBSR units undergo pre-shipment inspection (PSI). If there is an issue with S32K338GHT1MJBSR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The S32K338GHT1MJBSR part is unused and in its original packaging.
Return procedure for S32K338GHT1MJBSR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
S32K338GHT1MJBSR Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

