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NXP Semiconductors S32K338GHT1MJBST
- Part No.:
- S32K338GHT1MJBST
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 289-LFBGA
- Datasheet:
-
S32K338GHT1MJBST.pdf
- Description:
- S32K338GHT1MJBST
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
S32K338GHT1MJBST from NXP Semiconductors is an ASIL-B rated automotive microcontroller featuring three independent Arm Cortex-M7 cores operating at up to 240 MHz, 8 MB ECC-protected program flash, 1152 KB ECC SRAM (including 384 KB TCM), and support for CAN FD, Ethernet AVB/TSN, QuadSPI (up to 2 Gbps), and triple 12-bit ADCs. It targets high-integrity body control, domain controller, and gateway applications in harsh automotive environments.
For engineers reviewing the S32K338GHT1MJBST datasheet, S32K338GHT1MJBST pinout, S32K338GHT1MJBST application, or S32K338GHT1MJBST equivalent, key selection criteria include triple-core real-time determinism, ASIL-B functional safety compliance, integrated HSE-B security engine, 320 GPIO capability, and compatibility with S32K3xx software ecosystem and development tools.
Technical Context
The S32K338GHT1MJBST implements three independent Arm Cortex-M7 cores-each with FPU, DSP, I/D-cache, and zero-wait TCM-coordinated via a 64-bit crossbar fabric. Its memory subsystem includes 8 MB ECC flash, 1152 KB ECC SRAM (384 KB TCM), and QuadSPI interface supporting 8-bit data width at up to 2 Gbps for external memory expansion.
Safety architecture integrates FCCU, SWT timers, ECC/EDC on all memories and data paths, CRC module, XRDC access control, and Virtualization Wrapper (VIRT_WRAPPER). Communication subsystem delivers 8 FlexCAN (CAN FD), 16 LPUART, 6 LPSPI, 2 LPI2C, 2 SAI, and dual 100/1000 Mbps Ethernet with AVB/TSN support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Three independent Arm Cortex-M7 cores, each up to 240 MHz, with FPU, DSP, and dedicated TCM for deterministic real-time control loops. |
| Memory | 8 MB program flash with ECC; 1152 KB SRAM with ECC (384 KB TCM); supports RWW and A/B swap for robust OTA updates. |
| Operating Voltage | 2.97 V to 5.5 V - enables direct connection to automotive battery rail without intermediate regulation in many configurations. |
| Temperature Range | -40 °C to +125 °C - qualified for under-hood and chassis-mounted automotive applications across all power modes. |
| Functional Safety | ASIL-B compliant per ISO 26262; includes hardware redundancy, centralized error detection (FCCU), and memory ECC/EDC protection. |
| Security | HSE-B hardware security engine supporting AES-256, RSA-4096, ECC-521, side-channel protection, and upgradable firmware. |
| Networking | 8 FlexCAN channels (all CAN FD capable); dual Ethernet (100/1000 Mbps with AVB/TSN); 16 LPUART, 6 LPSPI, 2 LPI2C, 2 SAI. |
| Analog & Timing | Three 12-bit ADCs (24-channel each); three eMIOS modules (72 timer channels); BCTU for ADC/timer cross-triggering; 32-bit RTC with API. |
Pinout & Package
Package: MAPBGA437 (17 × 17 mm, 0.8 mm pitch) with exposed pad (EP) for thermal management. Pin count: 437 terminals. Compatible with standard reflow profiles for automotive-grade PCB assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_CORE | Core supply voltage | Provides regulated 1.1 V ±5% to CPU cores and internal logic; requires local low-ESR decoupling. |
| VDD_IO | I/O supply voltage | Supports 3.3 V or 5 V operation; configurable per bank to interface with legacy or mixed-voltage peripherals. |
| RESET_B | Active-low reset input | Asynchronous reset signal; internally synchronized and debounced; initiates full system reset sequence. |
| JTAG_TCK / SWD_CLK | Debug clock | Single-pin shared clock for SWD and JTAG debug interfaces; enables production programming and field diagnostics. |
| FXOSC_IN / FXOSC_OUT | External crystal oscillator interface | Accepts 8–40 MHz crystal; provides primary high-accuracy clock source for PLL and system timing. |
| ETH_RXD0–ETH_RXD3 | Ethernet receive data lines | 4-bit RMII/MII interface for 100 Mbps mode; supports TSN timestamping and AVB frame scheduling. |
| CAN0_TX / CAN0_RX | FlexCAN channel 0 differential signals | High-speed CAN FD transceiver interface (up to 5 Mbps); integrated bus termination and fault protection. |
Key Features
| Feature | Design Value |
|---|---|
| Triple independent M7 cores | Enables partitioned real-time workloads (e.g., comms stack, safety monitor, application logic) without lockstep overhead. |
| QuadSPI with 8-bit bus & 2 Gbps | Direct XIP-capable interface for fast external code/data execution; eliminates boot latency from serial NOR/NAND. |
| HSE-B with Evita Full compliance | Hardware-accelerated crypto and secure boot root-of-trust; meets AUTOSAR SecOC and Uptane requirements. |
| ASIL-B certified safety subsystem | FCCU, dual SWT, ECC/EDC, and XRDC collectively satisfy decomposition requirements for ASIL-B decomposition from ASIL-D systems. |
| 320 GPIO with wakeup/interrupt | 60 pins support wakeup from STANDBY; 32 pins support configurable interrupt generation; reduces need for external GPIO expanders. |
| BCTU cross-trigger unit | Hardware-synchronized triggering between ADC conversions and eMIOS PWM edges-critical for motor current sampling accuracy. |
Applications
| Body Control Module (BCM) | Automotive Gateway |
|---|---|
|
Use Scenario: Centralized control of lighting, door locks, window lifts, and HVAC actuators in modern vehicle architectures. IC Role / Device Role / Timing Role: Primary MCU executing ASIL-B-compliant control algorithms, managing LIN/CAN clusters, and coordinating power sequencing. Use Value: Triple-core isolation allows concurrent execution of safety-critical door-lock logic, non-critical ambient lighting PWM, and diagnostic communication-without software partitioning complexity. |
Use Scenario: High-bandwidth bridging between CAN FD, Ethernet TSN, and LIN domains in zonal E/E architectures. IC Role / Device Role / Timing Role: Real-time protocol translation engine with deterministic packet forwarding, time-synchronized message routing, and firewall-enforced domain separation. Use Value: Dual Ethernet ports + 8 CAN FD channels + 16 LPUART enable seamless integration of ADAS sensors, infotainment, and chassis ECUs while maintaining <10 µs inter-domain latency. |
| Electric Powertrain Controller | Domain Controller for ADAS Integration |
|
Use Scenario: Motor control and battery management coordination in 48 V mild-hybrid or BEV auxiliary systems. IC Role / Device Role / Timing Role: Real-time executor of FOC algorithms using BCTU-synchronized ADC sampling and eMIOS-generated PWM waveforms. Use Value: 384 KB TCM + triple M7 cores deliver sub-1 µs loop latency for torque control, while HSE-B secures over-the-air firmware updates for calibration parameters. |
Use Scenario: Sensor fusion hub aggregating camera, radar, and ultrasonic inputs for parking assistance and automated driving functions. IC Role / Device Role / Timing Role: Deterministic data aggregator with time-aligned timestamping across heterogeneous sensor interfaces (SAI, LPSPI, FlexIO-emulated protocols). Use Value: 2 Gbps QuadSPI enables local caching of neural network weights; triple ADCs and BCTU support synchronized multi-sensor analog preprocessing prior to AI inference offload. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| S32K344 | ASIL-D lockstep dual-core variant; identical package and peripheral set but with redundant core pair and enhanced safety mechanisms. | Required where ASIL-D decomposition mandates hardware redundancy (e.g., steering control), not suitable for cost-sensitive ASIL-B-only designs. | Select S32K344 only when functional safety target exceeds ASIL-B or when system-level decomposition requires lockstep verification. |
| S32K328 | Dual-core (not triple); same 8 MB flash and 1152 KB SRAM, but lacks third M7 core and associated TCM allocation. | Appropriate for gateway or domain controller roles requiring high throughput but not parallel real-time task partitioning. | Choose S32K328 when workload can be distributed across two cores and third-core determinism is unnecessary-reducing software complexity and BOM cost. |
Compared with S32K344, S32K338GHT1MJBST offers higher core concurrency at ASIL-B level, while S32K328 provides lower software overhead and reduced power consumption for dual-core-optimized firmware stacks-making S32K338GHT1MJBST optimal for tripartite workload isolation in next-gen vehicle domains.
Availability
S32K338GHT1MJBST is available at Aetrix Electronics and suitable for automotive body control modules, zonal gateways, electric powertrain controllers, and ADAS domain controllers requiring stable component supply, long lifecycle commitment, and AEC-Q100 Grade 1 qualification.
Supply support for S32K338GHT1MJBST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and automotive-grade MCUs.
The S32K3xx product line was designed specifically for next-generation automotive domain and zonal controllers-delivering scalable performance, ASIL-B/D safety certification, and hardware-enforced security in single-die solutions.
FAQ
What is the maximum operating frequency of the S32K338GHT1MJBST cores?
The S32K338GHT1MJBST features three independent Arm Cortex-M7 cores, each capable of operating at up to 240 MHz. This frequency is achievable across the full -40 °C to +125 °C ambient temperature range and 2.97 V to 5.5 V supply voltage, with all timing specifications guaranteed per the official NXP datasheet Rev. 14. The S32K338GHT1MJBST uses dual PLLs and optimized clock gating to maintain stability at this speed under automotive load conditions.
Does the S32K338GHT1MJBST support CAN FD, and how many channels are available?
Yes, the S32K338GHT1MJBST integrates eight FlexCAN modules, and all channels support CAN FD protocol with data rates up to 5 Mbps. Each channel includes built-in message RAM, acceptance filtering, and loopback/self-test modes. This capability is confirmed in the S32K3xx Data Sheet Rev. 14, Figure 11 block diagram and "Communications interfaces" section-making the S32K338GHT1MJBST suitable for high-bandwidth automotive backbone networks.
What package type and pin count does the S32K338GHT1MJBST use?
The S32K338GHT1MJBST is offered exclusively in the MAPBGA437 package: a 17 mm × 17 mm ball grid array with 437 solder balls, 0.8 mm pitch, and an exposed thermal pad (EP). This package is explicitly listed in the "I/O and package" section of the S32K3xx Data Sheet Rev. 14 and is used across all S32K338 variants for thermal and routing consistency in automotive PCB layouts.
Is the S32K338GHT1MJBST qualified for automotive use, and what is its AEC-Q100 grade?
Yes, the S32K338GHT1MJBST is AEC-Q100 qualified to Grade 1 (-40 °C to +125 °C), with full qualification documentation available from NXP. Its design, testing, and production follow automotive-specific process controls, and it meets ISO 26262 ASIL-B requirements out of the box-including hardware safety mechanisms, FMEDA reports, and safety manual support. This makes the S32K338GHT1MJBST appropriate for under-hood and chassis-mounted applications.
Does the S32K338GHT1MJBST include hardware security features beyond basic encryption acceleration?
Yes, the S32K338GHT1MJBST integrates the HSE-B (Hardware Security Engine-B) module, which provides AES-256, RSA-4096, and ECC-521 acceleration, secure boot with immutable root-of-trust, side-channel attack resistance, and upgradable firmware. It satisfies Evita Full security goals and supports AUTOSAR SecOC and Uptane-compliant OTA update frameworks-confirmed in the "Reliability, safety and security" section of the S32K3xx Data Sheet Rev. 14.
S32K338GHT1MJBST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 289-LFBGA
- Series:
- S32K3
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Tri-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, Ethernet, FlexIO, I2C, LINbus, QSPI, SAI, SENT, SPI, UART/USART
- Peripherals:
- DMA, I2S, WDT
- Number of I/O:
- 218
- Program Memory Size:
- 8MB (8M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 1.125M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.97V ~ 5.5V
- Data Converters:
- A/D 24x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
S32K338GHT1MJBST FAQ
1.How can I place an order for S32K338GHT1MJBST through Aetrix?
Please submit a Request for Quotation (RFQ) for S32K338GHT1MJBST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for S32K338GHT1MJBST reliable?
The price and inventory of S32K338GHT1MJBST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for S32K338GHT1MJBST is usually 5 days.
3.What payment methods are accepted for S32K338GHT1MJBST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for S32K338GHT1MJBST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for S32K338GHT1MJBST?
S32K338GHT1MJBST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your S32K338GHT1MJBST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for S32K338GHT1MJBST?
For technical support, including S32K338GHT1MJBST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your S32K338GHT1MJBST requirements.
6.How does Aetrix verify that S32K338GHT1MJBST is sourced from the original manufacturer or authorized distributors?
All S32K338GHT1MJBST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that S32K338GHT1MJBST meets industry standards.
7.What is the process for return or replacement of S32K338GHT1MJBST?
All S32K338GHT1MJBST units undergo pre-shipment inspection (PSI). If there is an issue with S32K338GHT1MJBST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The S32K338GHT1MJBST part is unused and in its original packaging.
Return procedure for S32K338GHT1MJBST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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