NXP Semiconductors S32K338GHT1MPCST
- Part No.:
- S32K338GHT1MPCST
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 172-QFP Exposed Pad
- Datasheet:
-
S32K338GHT1MPCST.pdf
- Description:
- S32K338GHT1MPCST
- Quantity:
- Payment:

- Shipping:

Inventory:3,778
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
S32K338GHT1MPCST from NXP Semiconductors is an ASIL-B certified, three-core Arm® Cortex-M7 automotive microcontroller operating up to 240 MHz, featuring 8 MB ECC-protected program flash, 1152 KB SRAM with 384 KB TCM, and integrated QuadSPI supporting up to 2 Gbps (8-bit data width) for external memory expansion. It delivers real-time deterministic control in body electronics, gateway, and domain controller applications requiring high I/O count, CAN FD networking, and Ethernet AVB/TSN.
For engineers reviewing the S32K338GHT1MPCST datasheet, S32K338GHT1MPCST pinout, S32K338GHT1MPCST application, or S32K338GHT1MPCST equivalent, key selection criteria include triple-core lockstep-capable architecture, 3× 12-bit ADCs (24-channel each), 8× FlexCAN modules with full CAN FD support, 1 Gbps Ethernet interface, and hardware security engine (HSE_B) with AES acceleration - all validated for automotive operation from −40 °C to 125 °C.
Technical Context
The S32K338GHT1MPCST implements three independent Arm Cortex-M7 cores at 240 MHz, each with FPU, DSP, and separate I/D cache, coordinated via a 64-bit crossbar fabric and shared memory subsystem. Its safety architecture includes centralized error detection (FCCU), memory ECC on all SRAM/flash, CRC modules, and dual PLLs for clock redundancy.
It integrates a comprehensive mixed-signal subsystem: three 24-channel 12-bit ADCs, three analog comparators with internal 8-bit DACs, BCTU for cross-triggering, and eMIOS timer modules offering 72 PWM/IC/OC channels. Communication is enabled by 8 FlexCAN (CAN FD), 16 LPUART, 6 LPSPI, 2 LPI2C, 2 SAI, and 1 Gbps Ethernet with AVB/TSN support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Three independent Arm Cortex-M7 @ 240 MHz, each with FPU, DSP, I/D cache, and zero-wait TCM |
| Memory | 8 MB program flash with ECC; 1152 KB SRAM with ECC, including 384 KB TCM for low-latency control loops |
| Operating Voltage | 2.97 V to 5.5 V - supports direct connection to automotive battery rails without external regulators |
| Temperature Range | −40 °C to +125 °C - qualified for under-hood and chassis-mounted automotive applications |
| Networking | 8× FlexCAN (all channels CAN FD capable); 1× 1 Gbps Ethernet with AVB/TSN; 16× LPUART with LIN support |
| Analog Peripherals | 3× 12-bit ADC (24 inputs each); 3× analog comparators with 8-bit DAC; BCTU for ADC/timer synchronization |
| Security & Safety | HSE_B hardware security engine (AES acceleration); ASIL-B compliance per ISO 26262; ECC on all memories; FCCU error management |
Pinout & Package
Package: MAPBGA437 (17 × 17 mm, 0.8 mm pitch, exposed thermal pad). This package supports high I/O density (up to 320 GPIO), thermal dissipation for sustained 240 MHz operation, and automotive-grade mechanical robustness.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA / VSSA | Analog power supply / ground | Isolated analog domain powering ADCs, comparators, and reference circuits; requires dedicated filtering |
| FXOSC_IN / FXOSC_OUT | External crystal oscillator interface | Supports 8–40 MHz crystals for precise system timing and clock source redundancy |
| ETH_RMII_RXD0–RXD1 / TXD0–TXD1 | Ethernet RMII data lines | Direct 10/100 Mbps Ethernet physical layer interface; no external PHY required for basic RMII operation |
| CAN0_TX / CAN0_RX – CAN7_TX / CAN7_RX | FlexCAN differential signal pairs | Eight fully independent CAN FD transceiver interfaces, each configurable for data rates up to 5 Mbps |
| QSPI_D0–D7 / QSPI_SCLK / QSPI_SS | QuadSPI data, clock, and chip select | 8-bit parallel interface enabling 2 Gbps external flash/RAM expansion with memory-mapped execution capability |
Key Features
| Feature | Design Value |
|---|---|
| Triple-core real-time processing | Three independent 240 MHz Cortex-M7 cores enable workload partitioning across safety-critical, communication, and application domains |
| Hardware Security Engine (HSE_B) | Integrated AES accelerator with side-channel protection and firmware-upgradable cryptographic stack meeting EVITA Full requirements |
| Automotive Ethernet AVB/TSN | 1 Gbps Ethernet MAC with time-sensitive networking support for synchronized sensor fusion and OTA update delivery |
| On-chip motor control subsystem | eMIOS timers (72 channels), BCTU, and LCU provide hardware-accelerated PWM generation and trigger coordination without CPU intervention |
| OTA-ready memory architecture | RWW (Read-While-Write) flash with A/B swap capability enables seamless field updates without system downtime |
Applications
| Body Control Module (BCM) | Vehicle Gateway |
|---|---|
Use Scenario: Centralized control of lighting, door locks, window lifts, and HVAC actuators in modern vehicle architectures. IC Role / Device Role / Timing Role: Primary real-time controller managing 320 GPIOs, 8 CAN FD buses, and 16 LPUARTs for distributed ECU communication. Use Value: Triple-core architecture isolates safety-critical functions (e.g., door unlock logic) from non-critical tasks (e.g., ambient lighting effects), ensuring ASIL-B compliance and deterministic response. |
Use Scenario: Aggregation and routing of messages between powertrain, chassis, infotainment, and ADAS domains over heterogeneous networks. IC Role / Device Role / Timing Role: High-throughput protocol translator bridging CAN FD, LIN, Ethernet AVB/TSN, and FlexIO-emulated interfaces. Use Value: Integrated 1 Gbps Ethernet and 8 FlexCAN modules eliminate external bridge ICs, reducing BOM cost and PCB area while maintaining <100 µs inter-domain latency. |
| Domain Controller (Body/Electrical) | Advanced Lighting Control Unit |
Use Scenario: Consolidation of multiple legacy ECUs into a single high-performance domain controller for electrical systems. IC Role / Device Role / Timing Role: Main compute engine executing AUTOSAR Classic/Adaptive stacks, managing memory protection (MPU), and enforcing XRDC-based access control. Use Value: 8 MB ECC flash and 1152 KB SRAM with TCM support complex middleware stacks and secure boot verification without external memory. |
Use Scenario: Dynamic LED matrix control with pixel-level dimming, diagnostics, and thermal management in adaptive front-lighting systems (AFS). IC Role / Device Role / Timing Role: Real-time PWM generator using eMIOS timers and BCTU-triggered ADC sampling for closed-loop current/voltage feedback. Use Value: Hardware-accelerated 72-channel eMIOS and 3× 12-bit ADCs enable sub-microsecond PWM update cycles and simultaneous multi-string current monitoring. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| S32K344 | ASIL-D lockstep dual-core Cortex-M7 @ 160 MHz; 4 MB flash; no Ethernet; 6 FlexCAN | Targeted at safety-critical powertrain/safety ECUs requiring higher ASIL rating but lower bandwidth | Select when functional safety certification to ASIL-D is mandatory and Ethernet/3-core throughput is not required |
| S32K328 | ASIL-B dual-core Cortex-M7 @ 240 MHz; 8 MB flash; 1 Gbps Ethernet; 8 FlexCAN; no third core | Optimized for gateway/domain controller roles needing high bandwidth but less parallel task isolation than triple-core | Choose when dual-core determinism suffices and third-core overhead is unnecessary for target software partitioning |
Compared with S32K344 and S32K328, the S32K338GHT1MPCST uniquely provides three independent high-frequency cores for strict hardware-enforced domain isolation, making it optimal for consolidated domain controllers where concurrent real-time, safety, and communication workloads must be physically separated without software scheduling risk.
Availability
S32K338GHT1MPCST is available at Aetrix Electronics and suitable for automotive body control modules, vehicle gateways, domain controllers, and advanced lighting systems requiring stable component supply across extended production lifecycles.
Supply support for S32K338GHT1MPCST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, and IoT applications, delivering secure, energy-efficient, and scalable silicon solutions.
The S32K3xx product line was designed specifically for next-generation automotive electrical/electronic (E/E) architectures, emphasizing ASIL-B/D compliance, hardware-based security, and consolidation of distributed functions into high-integration domain controllers.
FAQ
What is the maximum operating frequency of the S32K338GHT1MPCST?
The S32K338GHT1MPCST features three independent Arm Cortex-M7 cores, each operating at up to 240 MHz. This frequency is supported across the full −40 °C to +125 °C ambient temperature range and 2.97 V to 5.5 V supply voltage, verified per automotive qualification standards. All performance specifications for cache, TCM, and peripheral timing assume operation at this maximum frequency.
Does the S32K338GHT1MPCST support CAN FD, and how many channels are available?
Yes, the S32K338GHT1MPCST integrates eight FlexCAN modules, and all channels support CAN FD with data rates up to 5 Mbps. Each module operates independently with configurable bit timing, message RAM, and error counters, enabling simultaneous communication across multiple vehicle domains without arbitration bottlenecks.
What package type is used for the S32K338GHT1MPCST, and what are its thermal characteristics?
The S32K338GHT1MPCST is packaged in a MAPBGA437 (17 mm × 17 mm, 0.8 mm pitch) with an exposed thermal pad. This package achieves a junction-to-board thermal resistance (ψJB) of 3.5 °C/W and supports continuous 240 MHz operation under automotive thermal conditions when mounted on a 4-layer PCB with adequate copper pour and thermal vias.
Is the S32K338GHT1MPCST qualified for automotive safety standards?
Yes, the S32K338GHT1MPCST is certified to ASIL-B per ISO 26262:2018. Its safety features include hardware error correction (ECC on all memories), centralized fault collection (FCCU), lockstep-capable architecture, memory protection unit (MPU), and extended cross-domain controller (XRDC) for master access rights enforcement - all documented in the official NXP safety manual.
What security features does the S32K338GHT1MPCST include beyond basic HSE_B?
Beyond the HSE_B hardware security engine (supporting AES-256, RSA-4096, ECC-521), the S32K338GHT1MPCST includes virtualization wrapper (VIRT_WRAPPER) for I/O protection, 64-bit unique ID, TRNG/PRNG, lifecycle management, side-channel physical protection, and EVITA Full-compliant firmware architecture - enabling secure boot, key provisioning, and OTA update authentication.
S32K338GHT1MPCST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 172-QFP Exposed Pad
- Series:
- S32K3
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M7
- Core Size:
- 32-Bit Tri-Core
- Speed:
- 240MHz
- Connectivity:
- CANbus, Ethernet, FlexIO, I2C, LINbus, QSPI, SAI, SENT, SPI, UART/USART
- Peripherals:
- DMA, I2S, WDT
- Number of I/O:
- 142
- Program Memory Size:
- 8MB (8M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 1.125M x 8
- Voltage - Supply (Vcc/Vdd):
- 2.97V ~ 5.5V
- Data Converters:
- A/D 24x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
S32K338GHT1MPCST FAQ
1.How can I place an order for S32K338GHT1MPCST through Aetrix?
Please submit a Request for Quotation (RFQ) for S32K338GHT1MPCST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for S32K338GHT1MPCST reliable?
The price and inventory of S32K338GHT1MPCST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for S32K338GHT1MPCST is usually 5 days.
3.What payment methods are accepted for S32K338GHT1MPCST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for S32K338GHT1MPCST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for S32K338GHT1MPCST?
S32K338GHT1MPCST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your S32K338GHT1MPCST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for S32K338GHT1MPCST?
For technical support, including S32K338GHT1MPCST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your S32K338GHT1MPCST requirements.
6.How does Aetrix verify that S32K338GHT1MPCST is sourced from the original manufacturer or authorized distributors?
All S32K338GHT1MPCST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that S32K338GHT1MPCST meets industry standards.
7.What is the process for return or replacement of S32K338GHT1MPCST?
All S32K338GHT1MPCST units undergo pre-shipment inspection (PSI). If there is an issue with S32K338GHT1MPCST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The S32K338GHT1MPCST part is unused and in its original packaging.
Return procedure for S32K338GHT1MPCST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
S32K338GHT1MPCST Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

