NXP Semiconductors SAA7105E/V1/G,518

Overview

SAA7105E/V1/G,518 from NXP Semiconductors (formerly Philips Semiconductors) is a monolithic 3.3 V CMOS digital video encoder IC with integrated triple 10-bit DACs, programmable horizontal/vertical scaler, and 5-line anti-flicker filter. It converts non-interlaced RGB or 4:2:2 Y-CB-CR graphics data up to 1280 × 1024 @ 60 Hz into PAL/NTSC CVBS, S-video, or RGB-SCART analog outputs. Designed for PC-to-TV video bridging in embedded graphics systems.

For engineers reviewing the SAA7105E/V1/G,518 datasheet, SAA7105E/V1/G,518 pinout, SAA7105E/V1/G,518 application, or SAA7105E/V1/G,518 equivalent, key selection considerations include its 27 MHz crystal-stable subcarrier generation, 85 MHz maximum pixel clock support, I²C-bus programmability (400 kHz), 5 V-tolerant I/Os, and hardware cursor overlay capability.

Technical Context

The SAA7105E/V1/G,518 implements a full digital video encoding pipeline: input formatter accepts RGB or Y-CB-CR at up to 85 MHz double-edged clocking; RGB-to-Y-CB-CR matrix includes gain adjustment for 0–255 to 16–235 level mapping; horizontal scaler supports 50–400% scaling with 12-bit phase resolution; vertical scaler performs re-interlacing with programmable YSKIP-based anti-flicker filtering.

Its encoder block generates crystal-locked (13.5 MHz base, 27 MHz DAC sampling) luminance and chrominance signals compliant with RS-170-A and ITU-R BT.470-3; triple DACs output CVBS, S-video (Y/C), or RGB+sync with adjustable levels; on-chip 27 MHz oscillator accepts fundamental or 3rd-harmonic crystals; boundary scan (JTAG IEEE 1149.1) enables production testability.

Key Specifications

Pinout & Package

Package: BGA156 (SOT472-1), 15 × 15 × 1.15 mm body, 156-ball array.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar digital video encoder applications.

Compared with ADV7170KSTZ and THS8200IPFP, the SAA7105E/V1/G,518 uniquely integrates scaler, anti-flicker filter, hardware cursor, teletext encoder, and JTAG testability - making it the only option for full-featured PC-to-TV bridging with minimal external components.

Availability

SAA7105E/V1/G,518 is available at Aetrix Electronics and suitable for PC graphics adapters, embedded kiosks, industrial HMIs, and broadcast monitoring equipment requiring stable component supply and long-term lifecycle support.

Supply support for SAA7105E/V1/G,518 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company formed from the spin-off of Philips Semiconductors in 2006, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

The SAA7105E/V1/G,518 belongs to NXP's legacy video processing product line, designed specifically for high-fidelity PC-to-analog video bridging in cost-sensitive embedded graphics systems with strict EMI and layout constraints.

FAQ

What video standards does the SAA7105E/V1/G,518 support?

The SAA7105E/V1/G,518 supports NTSC M and PAL B/G standards with crystal-stable subcarrier generation at 13.5 MHz base rate. It delivers compliant CVBS, S-video (Y/C), and RGB-SCART outputs meeting RS-170-A and ITU-R BT.470-3 specifications. The device also supports HDTV timing for 1920×1080i and 1280×720p, including 3-level sync pulses required for broadcast-grade monitors. All outputs are generated from its integrated 27 MHz oscillator and triple 10-bit DACs.

Does the SAA7105E/V1/G,518 require an external crystal?

Yes, the SAA7105E/V1/G,518 requires a 27 MHz crystal connected to XTALI and XTALO pins. It supports both fundamental-mode and 3rd-harmonic 27 MHz crystals, eliminating the need for external clock generators or PLLs. The on-chip oscillator drives the video encoder, DACs (in standard mode), and I²C-bus control block. In auxiliary VGA or HDTV modes, the DACs are clocked by PIXCLK instead of the crystal oscillator.

Can the SAA7105E/V1/G,518 generate RGB output with separate sync signals?

Yes, the SAA7105E/V1/G,518 can generate RGB output with separate sync signals via its HSM_CSYNC and VSM pins. When configured in bypass mode, it routes non-interlaced RGB input directly to the triple DACs and outputs TTL-level horizontal and vertical syncs suitable for driving a second VGA monitor. HSM_CSYNC can be advanced up to 31 periods of the 27 MHz clock to align with TV set RGB processing latency, ensuring stable display without tearing or jitter.

What is the function of the PD0–PD11 pins on the SAA7105E/V1/G,518?

The PD0–PD11 pins on the SAA7105E/V1/G,518 form a 12-bit parallel pixel data bus accepting RGB or Y-CB-CR input. In double-edge clocking mode, these pins handle 16-bit 4:2:2 data (e.g., ITU-R BT.656), with PD0–PD7 carrying LSB-to-MSB of one byte on the rising edge and PD4–PD11 carrying the next byte on the falling edge. Pin assignments are configurable via I²C registers SLOT and EDGE to match host graphics controller timing, supporting resolutions up to 1280×1024 @ 60 Hz.

How is teletext data inserted using the SAA7105E/V1/G,518?

Teletext data is inserted into the SAA7105E/V1/G,518 via the TTX_SRES pin, which accepts a WST or NABTS bitstream sampled at the 27 MHz crystal clock. At each rising edge of the TTXRQ_XCLKO2 output signal, one teletext bit must be presented at TTX_SRES after a programmable delay. Internally, the device performs phase-variant interpolation on the bitstream to minimize jitter before encoding into line 23 (PAL/50 Hz) or line 21 (NTSC/60 Hz). Configuration and data loading are managed through dedicated I²C registers.