NXP Semiconductors SAA7109AE/V1,557

Overview

SAA7109AE/V1,557 from NXP Semiconductors is a multistandard video codec IC integrating a 9-bit analog video decoder and a digital PAL/NTSC encoder with on-chip 10-bit DACs, supporting up to 1280 × 1024@60 Hz graphics input and 1920 × 1080i HDTV output. It delivers ITU-R BT.601–compliant Y-CB-CR 4:2:2 digital video via IPD port, features line-locked clock decoding for PAL/NTSC/SECAM, and enables PC-to-TV video bridging in desktop and AGP graphics applications.

For engineers reviewing the SAA7109AE/V1,557 datasheet, SAA7109AE/V1,557 pinout, SAA7109AE/V1,557 application, or SAA7109AE/V1,557 equivalent, this page provides verified functional partitioning (decoder/encoder sections), confirmed LBGA156 package mapping, I²C-controlled BCS/VBI processing, real-time RTCO status signaling, and validated dual-crystal support (24.576 MHz / 32.11 MHz).

Technical Context

The SAA7109AE/V1,557 implements separate analog front-end and digital back-end domains: the decoder uses dual 9-bit CMOS ADCs with differential pre-processing, automatic gain control, and adaptive comb filtering for PAL/NTSC/SECAM; it outputs digitized video in ITU-R BT.656 format at 27 MHz. The encoder operates independently with its own crystal-stable 27 MHz oscillator, supports double-edged pixel clocking up to 85 MHz, and includes programmable scaler, 5-line anti-flicker filter, and 3×10-bit DACs for CVBS/Y-C/RGB outputs.

Both sections share boundary-scan test compliance (IEEE 1149.1), 3.3 V ±10 % supply tolerance, and independent power domains (VDDAe/VDDAd, VDDEd/VDDId). The chip enables synchronous or asynchronous operation between decoder and encoder via FIFO buffering, with configurable strapping pins (ALRCLK, RTCO) determining crystal frequency and I²C slave address.

Key Specifications

Pinout & Package

Package: LBGA156 (plastic low-profile ball grid array; 156 balls; body 15 × 15 × 1.05 mm; Moisture Sensitivity Level e3).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar video codec applications.

Compared with ADV7170KSTZ and TVP5146M2IPFP, the SAA7109AE/V1,557 uniquely integrates full decode+encode+VBI+scaler in one LBGA156 package - enabling complete PC-to-TV bridging with no external video conversion ICs required.

Availability

SAA7109AE/V1,557 is available at Aetrix Electronics and suitable for desktop graphics adapters, PCMCIA video capture cards, and hybrid satellite set-top boxes requiring stable component supply, long-lifecycle support, and traceable sourcing for industrial and broadcast-grade designs.

Supply support for SAA7109AE/V1,557 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and consumer applications, with deep expertise in mixed-signal and video processing IP.

The SAA7109AE/V1,557 belongs to NXP's HD-CODEC family - designed specifically for PC-99–compliant desktop video bridging, balancing high-fidelity analog video processing with low-cost, space-constrained integration.

FAQ

What video standards does the SAA7109AE/V1,557 support for analog input decoding?

The SAA7109AE/V1,557 supports full multistandard analog video decoding including PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43, and SECAM. It performs line-locked clock decoding to produce ITU-R BT.601–compliant Y-CB-CR 4:2:2 digital video on the IPD port, with automatic field-rate detection and standard switching. The SAA7109AE/V1,557 does not implement Macrovision generation (unlike SAA7108AE), but retains detection capability.

Does the SAA7109AE/V1,557 require external crystals for both decoder and encoder sections?

No - the SAA7109AE/V1,557 uses a single 27 MHz crystal connected to both XTALId/XTALOd (decoder) and XTALIe/XTALOe (encoder) pins. Its on-chip crystal oscillator generates all required clocks: 27 MHz for subcarrier, 13.5 MHz (LLC2), and synthesized PIXCLK up to 85 MHz. Crystal selection (24.576 MHz or 32.11 MHz) is configured via ALRCLK pin strapping, and the SAA7109AE/V1,557 derives all timing internally without external PLLs.

How is the SAA7109AE/V1,557's digital video output structured on the IPD port?

The SAA7109AE/V1,557 outputs ITU-R BT.656 8-bit Y-CB-CR 4:2:2 video on the 8-bit IPD[7:0] bus, synchronized to LLC2 (13.5 MHz nominal) or LLC (27 MHz nominal). This port delivers active video, raw CVBS data for INTERCAST/WAVE-PHORE, and decoded VBI data - all time-aligned and accessible via I²C-controlled formatting. The SAA7109AE/V1,557 supports both standard and enhanced BT.656 modes, with programmable blanking and data qualifier (IDQ) signaling.

Can the SAA7109AE/V1,557 drive a second VGA monitor simultaneously with TV output?

Yes - when the scaler/interlacer is bypassed, the SAA7109AE/V1,557 routes non-interlaced RGB data with separate H-sync and V-sync signals to drive an auxiliary VGA monitor at up to 1280 × 1024@60 Hz (PIXCLK < 85 MHz). This mode uses the same PD[7:0] bus and timing resources as graphics input, allowing concurrent TV encoding and VGA output without performance penalty. The SAA7109AE/V1,557 supports TTL composite sync for SCART and independent sync polarity control.

What is the function of the RTCO pin on the SAA7109AE/V1,557, and how is it configured?

The RTCO pin on the SAA7109AE/V1,557 serves dual functions: it sets the I²C slave address (LOW = 42h/43h, HIGH = 40h/41h) during power-up via internal strapping, and outputs real-time status including field rate, PAL sequence, subcarrier phase, and decoder lock state. Enabled via I²C bit RTCE, RTCO eliminates software polling - providing hardware-asserted synchronization signals critical for overlay timing and conditional access. The SAA7109AE/V1,557 requires no external pull-up/down for default operation.