NXP Semiconductors SAA7109AE/V1/G,557

Overview

SAA7109AE/V1/G,557 from NXP Semiconductors is a multistandard video decoder and encoder IC designed for PC-99-compliant desktop video applications. It integrates a 9-bit analog front-end decoder (supporting PAL BGHI/N/M, NTSC M/J/N/4.43, SECAM), a digital video scaler, and a 10-bit triple-DAC encoder delivering CVBS/S-video/RGB outputs at up to 1280×1024@60 Hz or 1920×1080i@60 Hz. Its dual I²C-bus control, line-locked decoding, and crystal-stable 27 MHz encoding enable simultaneous PC graphics-to-TV conversion in hybrid set-top boxes and AGP graphics cards.

For engineers reviewing the SAA7109AE/V1/G,557 datasheet, SAA7109AE/V1/G,557 pinout, SAA7109AE/V1/G,557 application, or SAA7109AE/V1/G,557 equivalent, key selection criteria include its dual-standard decode/encode capability, 156-ball LBGA package with boundary-scan support, 3.3 V CMOS operation, integrated 5-line anti-flicker filter, and real-time VBI data slicing for teletext/closed caption.

Technical Context

The SAA7109AE/V1/G,557 implements separate decoder and encoder subsystems with independent clock domains: the decoder uses line-locked PLL-based timing derived from incoming analog video (50/60 Hz field detection), while the encoder operates on a crystal-stable 27 MHz subcarrier clock-optionally slaved via FIFO buffering. Both sections share a unified 3.3 V supply architecture but maintain isolated analog/digital grounds (VDDAe/VSSAe, VDDAd/VSSAd) and dedicated I²C interfaces (SDAe/SCLe, SDAd/SCLd) for concurrent host control.

Its video processing pipeline includes two differential 9-bit ADC channels for analog input acquisition, adaptive comb filtering for NTSC cross-color reduction and PAL delay-line phase correction, programmable BCS/hue control, and a 27 MHz VBI data bypass path. The encoder supports non-interlaced RGB input (up to 4:4:4), hardware cursor overlay, and 3×256-byte LUT for gamma correction-all accessible via the Image Port Data (IPD) bus or I²C.

Key Specifications

Pinout & Package

Package: LBGA156 (plastic low-profile ball grid array; 15 × 15 × 1.05 mm body; 156 solder balls).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar video codec applications.

Compared with ADV7170KSTZ and TVP5150AM1IPBS, the SAA7109AE/V1/G,557 provides full bidirectional video processing in one LBGA package-reducing component count by two chips and enabling synchronized decode/encode timing critical for hybrid broadcast-PC systems.

Availability

SAA7109AE/V1/G,557 is available at Aetrix Electronics and suitable for desktop graphics adapters, hybrid satellite set-top boxes, and PC-based video editing stations requiring stable component supply and long-term industrial availability.

Supply support for SAA7109AE/V1/G,557 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and consumer applications.

The SAA7109AE/V1/G,557 belongs to NXP's HD-CODEC family-designed specifically for high-integration PC-99 video subsystems requiring simultaneous analog video acquisition and broadcast-standard output generation.

FAQ

What video standards does the SAA7109AE/V1/G,557 support for decoding and encoding?

The SAA7109AE/V1/G,557 supports PAL BGHI, PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43, and SECAM for decoding. For encoding, it outputs PAL (50 Hz) and NTSC (60 Hz) composite video, S-video, and RGB signals. Its auto-detection logic identifies field frequency and switches standards without host intervention-ensuring robust operation across global broadcast regions. All decoding and encoding functions are implemented within the same SAA7109AE/V1/G,557 die.

Does the SAA7109AE/V1/G,557 require separate crystals for decoder and encoder sections?

No-the SAA7109AE/V1/G,557 requires only one crystal (24.576 MHz or 32.11 MHz) for all standards. The decoder uses line-locked clock generation derived from incoming video sync, while the encoder employs an on-chip 27 MHz crystal oscillator (fundamental or 3rd harmonic). Pin ALRCLK strapping selects the crystal frequency during power-up reset, eliminating need for dual oscillators or external clock synthesis circuitry in the SAA7109AE/V1/G,557 design.

How does the SAA7109AE/V1/G,557 handle VBI data such as teletext and closed caption?

The SAA7109AE/V1/G,557 integrates a multistandard VBI data slicer capable of decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), and Vertical Interval Time Code (VITC). Decoded data appears on the IPD bus alongside active video, and raw 27 MHz VBI data is available via dedicated bypass path-enabling direct host CPU access without external demodulation. This functionality is fully operational in the SAA7109AE/V1/G,557 without firmware or external components.

What is the role of the TVD pin on the SAA7109AE/V1/G,557?

The TVD pin on the SAA7109AE/V1/G,557 is a dedicated open-drain hot-plug detection interrupt that asserts HIGH when a TV monitor is physically connected to the analog output. This signal enables the host system to dynamically reconfigure video routing, disable unused outputs, or trigger EDID-like handshaking-critical for seamless plug-and-play operation in desktop graphics cards and docking stations using the SAA7109AE/V1/G,557.

Can the SAA7109AE/V1/G,557 drive a second VGA monitor simultaneously with TV output?

Yes-the SAA7109AE/V1/G,557 supports auxiliary VGA monitor mode when the scaler/interlacer is bypassed. In this configuration, RGB outputs deliver non-interlaced graphics at up to 1280×1024@60 Hz with separate H/V-sync signals (VSM/HSM_CSYNC pins), while the encoder simultaneously drives CVBS/S-video to a TV. This dual-output capability is natively supported in hardware and requires no additional timing controllers or multiplexers in the SAA7109AE/V1/G,557 implementation.