Microchip Technology SAM9X60-V/DWB

Overview

SAM9X60-V/DWB from Microchip Technology is an ultra-low power ARM926EJ-S™ microprocessor unit (MPU) operating at 600 MHz, integrating dual 10/100 Ethernet MACs, two CAN controllers, LCD and 2D graphics controllers, QSPI, USB HS host/device, AES/SHA crypto accelerators, and a 12-bit ADC with touchscreen support. It targets industrial HMI, edge gateway, and secure embedded vision systems requiring real-time connectivity and tamper-resistant boot.

For engineers reviewing the SAM9X60-V/DWB datasheet, SAM9X60-V/DWB pinout, SAM9X60-V/DWB application, or SAM9X60-V/DWB equivalent, this page delivers verified technical context, validated package mapping, confirmed peripheral roles, exact clock domain assignments, and documented security feature implementation per FIPS PUB 180-2/197 and IEC 60730 Class B requirements.

Technical Context

The SAM9X60-V/DWB implements an ARM926EJ-S core with 32 KB instruction and 32 KB data caches plus MMU, supported by a multi-layer bus matrix enabling concurrent access to DDR2/LPDDR, NAND Flash (24-bit BCH ECC), and QSPI. Its system clock architecture includes two PLLs-one for general system operation and one optimized for USB HS (480 MHz)-and dual crystal oscillators (32.768 kHz and 12–48 MHz).

Peripherals are partitioned across dedicated bridges: LCDC and GFX2D share a DMA channel for overlay and alpha-blending; ISI supports ITU-R BT.601/656 12-bit image capture; EMAC0 uses MII/RMII while EMAC1 uses RMII only; and thirteen FLEXCOMs provide flexible USART/SPI/TWI configuration with programmable I/O multiplexing and Schmitt-trigger inputs.

Key Specifications

Pinout & Package

Package: 228-ball Thin Fine-Pitch Ball Grid Array (TFBGA), 11 mm × 11 mm, 0.65 mm ball pitch, optimized for 4-layer PCB layout with dedicated VDDCORE/VDDANA/VDDIOP0/VDDIN33 power domains and impedance-calibrated DDR/SDR PHY drivers.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MPU applications.

Compared with ATSAMA5D27-WD and i.MX6ULL, the SAM9X60-V/DWB uniquely combines dual 10/100 EMAC, two CAN 2.0B controllers, integrated ISI+GFX2D, and full FIPS PUB 180-2/197 compliance-making it optimal for industrial gateways requiring protocol diversity, real-time imaging, and certified security without external accelerators.

Availability

SAM9X60-V/DWB is available at Aetrix Electronics and suitable for industrial HMI, edge gateway, embedded vision, medical device, and smart energy applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SAM9X60-V/DWB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog components, FPGAs, and security solutions, with a focus on robust, low-power, and secure embedded systems for industrial, automotive, and IoT markets.

The SAM9X60 product line delivers ultra-low power ARM9-based MPUs targeting applications demanding high integration, deterministic real-time performance, hardware-enforced security, and extended temperature operation-especially where Linux-based HMI, secure connectivity, and vision processing converge.

FAQ

What is the maximum operating frequency of the SAM9X60-V/DWB CPU core?

The SAM9X60-V/DWB features an ARM926EJ-S processor core rated for operation up to 600 MHz. This frequency is achievable under specified thermal and voltage conditions (VDDCORE = 1.15 V, TA ≤ +105°C), and is supported by the integrated 32 KB instruction and 32 KB data caches plus MMU for efficient Linux execution. The SAM9X60-V/DWB datasheet confirms this rating in Section 1.1 and Table 1-1.

Does the SAM9X60-V/DWB support both MII and RMII Ethernet interfaces?

Yes, the SAM9X60-V/DWB supports MII and RMII on EMAC0, and RMII only on EMAC1. As documented in Table 1-1 and Section 3.1 of the DS60001579C datasheet, EMAC0 provides full MII/RMII capability for flexible PHY selection, while EMAC1 is RMII-only-enabling dual independent 10/100 Mbps connections with minimal pin count. This configuration is fixed per silicon design and cannot be reconfigured in software.

How does the SAM9X60-V/DWB implement secure boot and tamper protection?

The SAM9X60-V/DWB implements secure boot via a 64 KB ROM-resident bootloader configurable by OTP bits, supporting boot from NAND, SD card, SPI, or QSPI Flash. Tamper protection includes eight dedicated WKUP pins (WKUP1–WKUP8) that trigger immediate AES/TDES key erasure, scrambling key wipe, and GPBR clearing when enabled. These mechanisms are detailed in Sections 5.3 and 5.4 of the DS60001579C datasheet.

Which power management ICs are officially recommended for use with the SAM9X60-V/DWB?

Microchip recommends the MCP16502AE and MCP16501A PMICs for the SAM9X60-V/DWB. The MCP16502AE provides four 1 A DC-DC buck regulators and two 0.3 A LDOs, while the MCP16501A offers three 1 A bucks and one 0.3 A LDO in a smaller QFN24 package. Both integrate I²C control, leakage-free backup mode, and voltage rails matched to SAM9X60-V/DWB's VDDCORE (1.15 V), VDDIOP0 (3.3 V), and VDDANA (1.8 V) requirements.

What is the resolution and interface capability of the integrated ADC in the SAM9X60-V/DWB?

The SAM9X60-V/DWB integrates a single 12-bit successive approximation ADC with 12 input channels (AD0–AD11), including dedicated pins for 4-wire resistive touchscreen support (AD0XP_UL, AD1XM_UR, AD2YP_LL, AD3YM_SENSE). It supports programmable sampling rates up to 1 MSPS and features built-in plausibility checking for IEC 60730 Class B compliance, as specified in Section 5.3 and Table 5-1 of the DS60001579C datasheet.