NXP Semiconductors SC16C654BIA68,529
- Part No.:
- SC16C654BIA68,529
- Manufacturer:
- NXP Semiconductors
- Package:
- 68-LCC (J-Lead)
- Datasheet:
-
SC16C654BIA68,529.pdf
- Description:
- IC QUAD UART 64BYTE 68PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:4,201
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SC16C654BIA68 from NXP Semiconductors (formerly Philips) is a quad UART IC designed for high-throughput serial communication in industrial embedded systems. It delivers 4 independent asynchronous channels, 64-byte transmit/receive FIFOs, up to 5 Mbit/s data rate at 5 V/3.3 V, and supports both Intel (16-mode) and Motorola (68-mode) bus interfaces - used in multi-protocol industrial gateways requiring legacy RS-232/422/485 modem interface support.
For engineers reviewing the SC16C654BIA68 datasheet, SC16C654BIA68 pinout, SC16C654BIA68 application, or SC16C654BIA68 equivalent, key selection criteria include 64-byte FIFO depth, dual-bus interface flexibility, hardware/software flow control, IrDA encoding/decoding capability, and PLCC68 package compatibility with legacy board layouts.
Technical Context
The SC16C654BIA68 implements four fully independent UART channels sharing a common 8-bit bidirectional data bus and programmable address decoding logic. Each channel features separate transmit/receive shift registers, 64-byte FIFOs with error flags, and configurable framing (5–8 data bits, 1/1.5/2 stop bits, even/odd/no parity).
It integrates dual-mode bus interface logic (16-mode with individual CSA–CSD chip selects and INTA–INTD interrupts; 68-mode with shared CS, A3/A4 addressing, and wire-OR'd IRQ), programmable baud rate generator (DC to 5 Mbit/s), automatic RTS/CTS and Xon/Xoff flow control, and infrared encoder/decoder compliant with IrDA 1.0 physical layer standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channels | 4 independent UARTs - enables simultaneous RS-232/422/485 port expansion without external multiplexing. |
| Max Data Rate | 5 Mbit/s at 5 V or 3.3 V (3 Mbit/s at 2.5 V) - supports high-speed modem and industrial fieldbus backhaul links. |
| FIFO Depth | 64-byte TX/RX FIFO per channel - reduces CPU interrupt load by ~4× vs. 16C554 (16-byte FIFO), extending service intervals from 1.53 ms to 6.1 ms at 115.2 kbit/s. |
| Supply Voltage | 2.5 V / 3.3 V / 5 V operation - allows direct interfacing with mixed-voltage system buses and legacy 5 V controllers. |
| Interface Modes | Configurable Intel 16-mode (PLCC68 only) or Motorola 68-mode - ensures drop-in compatibility with existing 16C454/554 and 68C454/554 designs. |
| IrDA Support | Integrated IrDA 1.0 encoder/decoder - eliminates need for external SIR/FIR PHY components in infrared terminal applications. |
| Operating Temp | −40 °C to +85 °C - qualified for industrial automation, transportation, and outdoor communications equipment. |
Pinout & Package
SC16C654BIA68 is housed in a plastic leaded chip carrier (PLCC68) package with 68 leads, body size 24.2 mm × 24.2 mm × 4.06 mm (SOT188-2), suitable for through-hole or surface-mount assembly with standard reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 16/68 | Interface mode select input | Logic 1 = 16-mode (Intel bus); Logic 0 = 68-mode (Motorola bus); determines IOR/IOW vs. R/W, INTA–INTD vs. IRQ, and CSA–CSD vs. CS/A3/A4 mapping. |
| CSA–CSD | Individual chip select inputs (16-mode) | Active-low enables for UART channels A–D; allows discrete addressing without address decoding logic. |
| INTA–INTD | Independent interrupt outputs (16-mode) | Active-high per-channel interrupts - simplifies priority-based ISR handling in real-time OS environments. |
| TXA–TXD / RXA–RXD | Transmit/receive data I/O | Four full-duplex serial data paths; each supports start/stop/parity framing and false start-bit detection. |
| RTSA–RTSD / CTSA–CTSD | Hardware flow control outputs/inputs | Enables automatic RTS/CTS handshaking per channel when EFR[6:7] enabled - prevents buffer overrun in bursty traffic. |
| D0–D7 | 8-bit bidirectional data bus | 3-state TTL-compatible interface - connects directly to microcontroller data buses without level-shifting. |
| A0–A2 | Register address select inputs | Selects internal UART register (THR/RHR/IER/FCR/etc.) during read/write cycles in both 16- and 68-modes. |
| XTAL1/XTAL2 | Clock input/output | Supports crystal (1–24 MHz) or external clock source; CLKSEL pin selects 1× or 4× pre-scaler for baud rate generation. |
Key Features
| Feature | Design Value |
|---|---|
| 64-byte FIFO per channel | Reduces CPU interrupt frequency by factor of 4 vs. 16C554, enabling longer deterministic task scheduling windows in RTOS-based industrial controllers. |
| Auto hardware/software flow control | Eliminates software polling overhead: RTS/CTS signals are asserted automatically based on FIFO fill level, while Xon/Xoff characters are programmable per channel. |
| Dual bus interface (16/68 mode) | Single BOM supports both Intel- and Motorola-based host platforms - avoids redesign when migrating between MCU families like ARM9 (16-mode) and ColdFire (68-mode). |
| IrDA 1.0 encoder/decoder | On-chip SIR (Serial Infrared) physical layer implementation - removes external transceiver IC, saving PCB area and BOM cost in handheld diagnostic tools. |
| Sleep mode | Reduces quiescent current to <10 µA - extends battery life in portable modems and remote telemetry units operating intermittently. |
| Modem control pins (DSR/CD/RI/DTR) | Full set of industry-standard modem status/control signals per channel - enables direct connection to legacy RS-232 modems without external glue logic. |
Applications
| Industrial Serial Gateway | Legacy Equipment Retrofit |
|---|---|
Use Scenario: Aggregating data from multiple RS-485 field devices (PLCs, sensors, drives) into an Ethernet backbone via a Linux-based edge gateway. IC Role / Device Role / Timing Role: Quad UART provides four isolated serial ports with hardware flow control and 64-byte FIFOs to sustain 921.6 kbit/s per channel under CPU load. Use Value: Eliminates need for external FIFO buffers or multi-drop UART expanders; 64-byte depth ensures no frame loss during Linux kernel context switches. |
Use Scenario: Upgrading aging CNC machine tool controllers originally using ST16C454 to support higher-speed spindle feedback and HMI updates. IC Role / Device Role / Timing Role: Pin- and software-compatible replacement with enhanced FIFO and IrDA support for wireless operator panel pairing. Use Value: Enables 4× faster serial throughput without PCB redesign; retains identical PLCC68 footprint and 16-mode interface timing. |
| Multi-Protocol Modem Hub | Diagnostic Handheld Terminal |
Use Scenario: Cellular/LTE modem module integrating simultaneous PPP, AT command, GPS NMEA, and firmware update channels. IC Role / Device Role / Timing Role: Four UARTs handle concurrent AT command parsing (channel A), GPS data streaming (B), cellular stack logging (C), and secure OTA updates (D). Use Value: Independent FIFO trigger levels and per-channel interrupt masking allow prioritized servicing - e.g., GPS data processed before debug logs. |
Use Scenario: Portable field service tool communicating with automotive ECUs via ISO 9141, KWP2000, and UDS protocols over RS-232. IC Role / Device Role / Timing Role: UART channel A runs K-line (single-wire), B handles L-line, C manages CAN-to-serial bridge, D supports IrDA for wireless ECU pairing. Use Value: Integrated IrDA encoder/decoder replaces discrete IR transceiver, reducing component count and enabling contactless vehicle identification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ST16C654CJ68 | 64-byte FIFO, 5 V only, no 2.5 V/3.3 V support; lacks IrDA encoder/decoder; identical PLCC68 pinout and 16/68 mode logic. | Restricted to 5 V systems; cannot replace SC16C654BIA68 in mixed-voltage or infrared-enabled designs. | Select when legacy 5 V-only infrastructure prohibits voltage scaling and IrDA is unused. |
| TL16C754BPTR | 64-byte FIFO, 3.3 V only, supports auto RTS/CTS but no IrDA; HVQFN48 package (no PLCC68 option); different pin assignment for modem signals. | Requires PCB redesign due to 48-pin QFN footprint and missing PLCC68 variant; incompatible with through-hole legacy assemblies. | Choose for space-constrained 3.3 V designs where infrared is unnecessary and surface-mount assembly is preferred. |
Compared with ST16C654CJ68 and TL16C754BPTR, SC16C654BIA68 uniquely combines triple-voltage operation (2.5/3.3/5 V), PLCC68 legacy compatibility, and integrated IrDA - making it the sole option for retrofitting infrared-capable industrial gateways without layout changes.
Availability
SC16C654BIA68 is available at Aetrix Electronics and suitable for industrial serial gateways, legacy equipment retrofits, and multi-protocol modem hubs requiring stable component supply across extended product lifecycles.
Supply support for SC16C654BIA68 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors (originally Philips Semiconductors) is a global leader in high-performance mixed-signal ICs for industrial, automotive, and communication applications.
The SC16C654BIA68 belongs to NXP's legacy UART product line, engineered specifically for backward-compatible upgrades of 16C454/554-based systems while adding critical enhancements: deeper FIFOs, dual-voltage operation, and IrDA support for modern diagnostics.
FAQ
What is the maximum data rate supported by SC16C654BIA68?
The SC16C654BIA68 supports up to 5 Mbit/s at 5 V or 3.3 V supply, and up to 3 Mbit/s at 2.5 V. This performance is achieved using an external clock input; with a 24 MHz crystal, the maximum achievable rate is 1.5 Mbit/s. The SC16C654BIA68 datasheet confirms these limits in Section 6.9 and Table 10, specifying that baud rates scale linearly with clock frequency and are constrained by voltage-dependent internal timing margins.
Is SC16C654BIA68 pin-compatible with ST16C454?
Yes, the SC16C654BIA68 powers up functionally equivalent to the ST16C454 in 16-mode and is pin-compatible with ST16C654 and TL16C754. Its PLCC68 footprint matches ST16C454/554, and all control, data, and modem signal pins align electrically and physically. However, SC16C654BIA68 adds new pins (e.g., CLKSEL, 16/68) not present on ST16C454 - these are internally pulled up/down and do not affect basic compatibility.
Does SC16C654BIA68 support infrared communication?
Yes, the SC16C654BIA68 includes a fully integrated IrDA 1.0 encoder/decoder compliant with SIR (Serial Infrared) physical layer specifications. It supports 9.6 kbit/s to 115.2 kbit/s infrared data transmission without external components. This functionality is enabled via the Enhanced Feature Register (EFR) and operates independently per channel, confirmed in Sections 2 and 6.10 of the SC16C654BIA68 datasheet.
What package type is SC16C654BIA68 supplied in?
The SC16C654BIA68 is supplied exclusively in the plastic leaded chip carrier (PLCC68) package, designated SOT188-2, with 68 leads and dimensions of 24.2 mm × 24.2 mm × 4.06 mm. This package supports both through-hole and surface-mount assembly and is the only variant offering 16/68 interface mode selection and full modem pin availability across all four channels.
Can SC16C654BIA68 operate at 2.5 V, and what are the trade-offs?
Yes, the SC16C654BIA68 is fully specified for 2.5 V operation across the industrial temperature range (−40 °C to +85 °C). At 2.5 V, the maximum data rate is reduced to 3 Mbit/s (vs. 5 Mbit/s at 5 V/3.3 V), and certain features like IrDA encoding require verification of signal rise/fall times per application. All logic thresholds and timing parameters remain guaranteed per the SC16C654BIA68 datasheet's 2.5 V electrical characteristics table.
SC16C654BIA68,529 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 68-LCC (J-Lead)
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Features:
- -
- Number of Channels:
- 4, QUART
- FIFO's:
- 64 Byte
- Protocol:
- -
- Data Rate (Max):
- 5Mbps
- Voltage - Supply:
- 2.5V, 3.3V, 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- Yes
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 68-PLCC (24.18x24.18)
SC16C654BIA68,529 FAQ
1.How can I place an order for SC16C654BIA68,529 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16C654BIA68,529 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16C654BIA68,529 reliable?
The price and inventory of SC16C654BIA68,529 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16C654BIA68,529 is usually 5 days.
3.What payment methods are accepted for SC16C654BIA68,529?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC16C654BIA68,529 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SC16C654BIA68,529?
SC16C654BIA68,529 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC16C654BIA68,529 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16C654BIA68,529?
For technical support, including SC16C654BIA68,529 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16C654BIA68,529 requirements.
6.How does Aetrix verify that SC16C654BIA68,529 is sourced from the original manufacturer or authorized distributors?
All SC16C654BIA68,529 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16C654BIA68,529 meets industry standards.
7.What is the process for return or replacement of SC16C654BIA68,529?
All SC16C654BIA68,529 units undergo pre-shipment inspection (PSI). If there is an issue with SC16C654BIA68,529, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16C654BIA68,529 part is unused and in its original packaging.
Return procedure for SC16C654BIA68,529:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SC16C654BIA68,529 Tags

-
SC16IS741AIPWJ
NXP Semiconductors

-
TL16C550CPTR
Texas Instruments

-
TL16C550CIPTR
Texas Instruments

-
SC16C752BIB48,128
NXP Semiconductors

-
ST16C2550CQ48-F
MaxLinear, Inc.

-
ST16C2550CJ44-F
MaxLinear, Inc.

-
ST16C2552CJ44-F
MaxLinear, Inc.

-
ST16C1550IQ48-F
MaxLinear, Inc.

-
ST16C2550IQ48-F
MaxLinear, Inc.

-
ST16C554DIQ64-F
MaxLinear, Inc.

-
ST16C554DCQ64-F
MaxLinear, Inc.
-
XR17V352IB113-F
MaxLinear, Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

