NXP Semiconductors SC16C750BIBS,128
- Part No.:
- SC16C750BIBS,128
- Manufacturer:
- NXP Semiconductors
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SC16C750BIBS,128.pdf
- Description:
- IC UART 64BYTE 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,860
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Product details
Overview
SC16C750BIBS,128 from NXP Semiconductors is a single-channel 5 V/3.3 V/2.5 V UART IC with 64-byte transmit and receive FIFOs, programmable auto-RTS/CTS hardware flow control, and support for serial data rates up to 3 Mbit/s at 5 V. It serves as a parallel-to-serial/serial-to-parallel bridge in embedded communication interfaces, enabling high-throughput RS-232/RS-485 modem and industrial control links.
For engineers reviewing the SC16C750BIBS,128 datasheet, SC16C750BIBS,128 pinout, SC16C750BIBS,128 application, or SC16C750BIBS,128 equivalent, this device delivers deterministic interrupt latency via four selectable FIFO trigger levels, DMA-ready TXRDY/RXRDY signaling, and sleep-mode power reduction - critical for real-time serial gateway and multi-protocol controller designs.
Technical Context
The SC16C750BIBS,128 implements a register-mapped UART core with dual 64-byte FIFOs, independent TX/RX baud rate generation (via 16× clock division), and full modem control logic (RTS/CTS/DSR/DTR/RI/DCD). Its internal loopback mode enables on-chip diagnostics without external wiring.
Hardware flow control operates via dedicated CTS input (to suspend transmission) and RTS output (driven by receive FIFO threshold logic), while sleep mode disables the oscillator upon IER[4] activation and wakes on start-bit detection or modem pin transitions - reducing quiescent current without firmware intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply voltage | 2.5 V, 3.3 V, or 5 V ±10 % - supports mixed-voltage system integration without level shifters |
| Max data rate | 3 Mbit/s at 5 V (48 MHz crystal); 2 Mbit/s at 3.3 V; 1 Mbit/s at 2.5 V - enables high-speed modem and industrial link operation |
| FIFO depth | 64-byte transmit + 64-byte receive FIFO with error flags - reduces CPU interrupt load by >75 % vs. 16C450 |
| FIFO trigger levels | Four selectable receive interrupt thresholds (1/16/32/56 bytes) - allows precise latency/bandwidth trade-off tuning |
| Flow control | Programmable auto-RTS and auto-CTS - eliminates software polling and enables zero-CPU-overhead serial streaming |
| Operating temperature | −40 °C to +85 °C - qualified for industrial and automotive under-hood environments |
| Package | HVQFN32 (5 × 5 × 0.85 mm, no leads) - enables compact PCB layout with thermal pad for power dissipation |
Pinout & Package
HVQFN32 package: 32-terminal thermally enhanced very thin quad flat no-lead package, body size 5 mm × 5 mm × 0.85 mm, exposed thermal pad, lead-free and RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D0–D7 | Data bus I/O | 8-bit bidirectional parallel interface to CPU/microcontroller; 3-state TTL drive for bus sharing |
| A0–A2 | Register address select | Selects among 12 internal registers (THR/RHR/IER/FCR/LCR/MCR/etc.) during read/write cycles |
| CS | Chip select | Active-low enable for register access; decodes UART from shared peripheral bus |
| IOR / IOW | Read/write strobe | Asynchronous control signals for CPU-initiated register reads/writes; compatible with ISA-style timing |
| TX / RX | Serial data I/O | Full-duplex asynchronous serial interface; TX drives composite serial output, RX accepts serial input |
| RTS / CTS | Hardware flow control | RTS output controlled by receive FIFO level; CTS input halts transmission on remote buffer full signal |
| INT | Interrupt output | Active-high prioritized interrupt signaling for RX ready, TX empty, line errors, or modem status change |
| RCLK / XTAL1 / XTAL2 | Timing inputs | RCLK accepts external 16× receiver clock; XTAL1/XTAL2 support crystal (1.8432–48 MHz) or external clock source |
| TXRDY / RXRDY | DMA handshake | Ready signals for DMA controllers: TXRDY active when transmit FIFO not full; RXRDY active when receive FIFO ≥ trigger level |
| RESET | Master reset | Active-high synchronous reset that clears registers and initializes outputs to known states |
| VCC / GND | Power supply | Single-supply operation at 2.5 V/3.3 V/5 V; GND pin 13 provides low-impedance return path for analog/digital sections |
Key Features
| Feature | Design Value |
|---|---|
| Auto-RTS/CTS flow control | Hardware-managed RTS assertion based on receive FIFO fill level and CTS-driven TX suspension - eliminates CPU polling overhead |
| Sleep mode | Reduces power consumption by disabling internal oscillator; wakes automatically on RX start bit, modem pin transition, or TX request |
| Internal loopback test | Enables full TX/RX path validation without external cabling - isolates UART core faults from physical layer issues |
| Programmable character format | Supports 5–8-bit words, 1/1.5/2 stop bits, even/odd/no parity - ensures interoperability with legacy and custom serial protocols |
| False start-bit detection | Rejects spurious noise-induced start bits before sampling - improves robustness in electrically noisy industrial environments |
Applications
| Industrial PLC Serial Gateway | Medical Device RS-232 Interface |
|---|---|
Use Scenario: Connecting multiple fieldbus devices (Modbus RTU, Profibus DP slaves) to a central PLC CPU via isolated RS-232/485 links. IC Role / Device Role / Timing Role: UART bridge converting CPU parallel bus transactions into time-critical serial frames with deterministic interrupt latency. Use Value: 64-byte FIFOs and auto-CTS prevent frame loss during burst transfers; sleep mode cuts standby power in battery-backed controllers. | Use Scenario: Enabling bidirectional patient data logging between ECG monitor and hospital network via RS-232-connected PC interface. IC Role / Device Role / Timing Role: Reliable serial data converter handling variable-length diagnostic packets with guaranteed delivery timing. Use Value: Four FIFO trigger levels allow tuning for low-latency ECG waveform streaming; false start-bit rejection prevents misreads in EM-interfered clinical settings. |
| POS Terminal Modem Link | Automotive Telematics ECU |
Use Scenario: Supporting dial-up credit card authorization via integrated V.34 modem in retail point-of-sale terminals. IC Role / Device Role / Timing Role: High-speed UART managing 3 Mbit/s modem handshaking and compressed data bursts under strict PCI compliance timing. Use Value: 3 Mbit/s capability at 5 V meets V.34 spec; auto-RTS/CTS ensures zero packet loss during peak transaction loads. | Use Scenario: Providing debug console and OTA firmware update channel between vehicle infotainment MCU and cellular module. IC Role / Device Role / Timing Role: Robust serial interface operating across −40 °C to +85 °C under hood conditions with minimal power draw. Use Value: Industrial temp range and sleep mode ensure reliable boot-time diagnostics and low-quiescent update sessions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar UART applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TL16C750IPM | Same 64-byte FIFOs and auto-flow control, but only 5 V operation; PLCC44 package; no 2.5 V/3.3 V support | Restricted to legacy 5 V systems; lacks multi-voltage flexibility for modern mixed-signal designs | Select TL16C750IPM only if board uses 5 V exclusively and PLCC44 footprint is fixed |
| SC16C752BIBS,128 | Dual-channel version in same HVQFN32 package; shares identical register map and FIFO architecture per channel | Enables two independent serial links (e.g., debug + modem) without doubling board area or BOM count | Choose SC16C752BIBS,128 when dual UART functionality is required and space-constrained layout permits |
Compared with TL16C750IPM, SC16C750BIBS,128 adds 2.5 V/3.3 V operation and HVQFN32 packaging for compact, low-power designs; versus SC16C752BIBS,128, it offers lower cost and simpler driver integration for single-link applications.
Availability
SC16C750BIBS,128 is available at Aetrix Electronics and suitable for industrial PLC gateways, medical device interfaces, POS terminal modems, and automotive telematics ECUs requiring stable component supply across extended temperature ranges and multi-voltage platforms.
Supply support for SC16C750BIBS,128 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The SC16C750BIBS,128 belongs to NXP's legacy UART product line designed for high-reliability serial communication in resource-constrained embedded systems requiring deterministic timing and low-power operation.
FAQ
What voltage levels does the SC16C750BIBS,128 support?
The SC16C750BIBS,128 operates at 2.5 V, 3.3 V, or 5 V ±10 %, with 5 V tolerance on input-only pins (D7–D0). This multi-voltage capability allows direct integration into mixed-supply systems without external level shifters, simplifying design for industrial and automotive applications where supply rails vary across subsystems. The SC16C750BIBS,128 maintains full functionality-including 3 Mbit/s data rate and 64-byte FIFO operation-across all supported voltages.
How does the auto-CTS feature work in the SC16C750BIBS,128?
In auto-CTS mode, the SC16C750BIBS,128 monitors the CTS input pin and automatically suspends transmission when CTS transitions LOW, indicating remote buffer full condition. Transmission resumes only after CTS returns HIGH. This hardware flow control eliminates software polling, reduces CPU overhead, and guarantees zero data loss during high-throughput transfers - a key advantage over basic 16C450-compatible UARTs. The SC16C750BIBS,128 implements this using dedicated internal logic synchronized to the transmitter clock domain.
What is the purpose of the TXRDY and RXRDY pins on the SC16C750BIBS,128?
TXRDY and RXRDY are active-low DMA handshake signals on the SC16C750BIBS,128. TXRDY asserts when the transmit FIFO is not full, enabling continuous DMA writes; RXRDY asserts when the receive FIFO reaches its programmed trigger level, signaling valid data for DMA reads. Both support two DMA modes (single- or multi-transfer) selected via FCR[3], allowing flexible memory-mapped data movement without CPU intervention. These pins directly interface with standard DMA controllers in microcontrollers and SoCs.
Can the SC16C750BIBS,128 operate with an external clock instead of a crystal?
Yes, the SC16C750BIBS,128 accepts an external clock up to 48 MHz applied to the XTAL1 pin, bypassing the internal crystal oscillator. This allows precise baud rate generation for custom frequencies and eliminates crystal load capacitance matching. When using external clocking, XTAL2 is left floating. The SC16C750BIBS,128's baud rate generator divides this input by 16× to derive the serial bit clock, supporting deterministic timing in systems where crystal stability is impractical or where clock sources are centrally distributed.
Does the SC16C750BIBS,128 support sleep mode, and how is it activated?
Yes, the SC16C750BIBS,128 includes a low-power sleep mode activated by setting bit 4 (SLEEP) in the Interrupt Enable Register (IER). In sleep mode, the internal oscillator is disabled, reducing current draw significantly. The SC16C750BIBS,128 wakes automatically on detection of a start bit on RX, state change on RI/CTS/DSR/DCD, or when transmit data is written to THR - enabling energy-efficient operation in battery-powered or thermally constrained applications without firmware wake-up routines.
SC16C750BIBS,128 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VFQFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Features:
- -
- Number of Channels:
- 1, UART
- FIFO's:
- 64 Byte
- Protocol:
- -
- Data Rate (Max):
- 3Mbps
- Voltage - Supply:
- 2.5V, 3.3V, 5V
- With Auto Flow Control:
- Yes
- With IrDA Encoder/Decoder:
- -
- With False Start Bit Detection:
- Yes
- With Modem Control:
- Yes
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-HVQFN (5x5)
SC16C750BIBS,128 FAQ
1.How can I place an order for SC16C750BIBS,128 through Aetrix?
Please submit a Request for Quotation (RFQ) for SC16C750BIBS,128 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SC16C750BIBS,128 reliable?
The price and inventory of SC16C750BIBS,128 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SC16C750BIBS,128 is usually 5 days.
3.What payment methods are accepted for SC16C750BIBS,128?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SC16C750BIBS,128 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SC16C750BIBS,128?
SC16C750BIBS,128 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SC16C750BIBS,128 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SC16C750BIBS,128?
For technical support, including SC16C750BIBS,128 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SC16C750BIBS,128 requirements.
6.How does Aetrix verify that SC16C750BIBS,128 is sourced from the original manufacturer or authorized distributors?
All SC16C750BIBS,128 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SC16C750BIBS,128 meets industry standards.
7.What is the process for return or replacement of SC16C750BIBS,128?
All SC16C750BIBS,128 units undergo pre-shipment inspection (PSI). If there is an issue with SC16C750BIBS,128, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SC16C750BIBS,128 part is unused and in its original packaging.
Return procedure for SC16C750BIBS,128:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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